netdev - RE: [RFC PATCH 0/3] kernel: add support for 256-bit IO access

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Date:   Thu, 22 Mar 2018 12:48:50 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Linus Torvalds' <torvalds@...ux-foundation.org>,
        'Ingo Molnar' <mingo@...nel.org>
CC:     'Thomas Gleixner' <tglx@...utronix.de>,
        'Rahul Lakkireddy' <rahul.lakkireddy@...lsio.com>,
        "'x86@...nel.org'" <x86@...nel.org>,
        "'linux-kernel@...r.kernel.org'" <linux-kernel@...r.kernel.org>,
        "'netdev@...r.kernel.org'" <netdev@...r.kernel.org>,
        "'mingo@...hat.com'" <mingo@...hat.com>,
        "'hpa@...or.com'" <hpa@...or.com>,
        "'davem@...emloft.net'" <davem@...emloft.net>,
        "'akpm@...ux-foundation.org'" <akpm@...ux-foundation.org>,
        "'ganeshgr@...lsio.com'" <ganeshgr@...lsio.com>,
        "'nirranjan@...lsio.com'" <nirranjan@...lsio.com>,
        "'indranil@...lsio.com'" <indranil@...lsio.com>,
        'Andy Lutomirski' <luto@...nel.org>,
        'Peter Zijlstra' <a.p.zijlstra@...llo.nl>,
        'Fenghua Yu' <fenghua.yu@...el.com>,
        'Eric Biggers' <ebiggers3@...il.com>
Subject: RE: [RFC PATCH 0/3] kernel: add support for 256-bit IO access

From: David Laight
> Sent: 22 March 2018 10:36
...
> Any code would need to be in memcpy_fromio(), not in every driver that
> might benefit.
> Then fallback code can be used if the registers aren't available.
> 
> >  (b) we can't guarantee that %ymm register write will show up on any
> > bus as a single write transaction anyway
> 
> Misaligned 8 byte accesses generate a single PCIe TLP.
> I can look at what happens for AVX2 transfers later.
> I've got code that mmap()s PCIe addresses into user space, and can
> look at the TLP (indirectly through tracing on an fpga target).
> Just need to set something up that uses AVX copies.

On my i7-7700 reads into xmm registers generate 16 byte TLP and
reads into ymm registers 32 byte TLP.
I don't think I've a system that supports avx-512

With my lethargic fpga slave 32 bytes reads happen every 144 clocks
and 16 byte ones every 126 (+/- the odd clock).
Single bytes ones happen every 108, 8 byte 117.
So I have (about) 110 clock overhead on every read cycle.
These clocks are the 62.5MHz clock on the fpga.

So if we needed to do PIO reads using the AVX2 (or better AVX-512)
registers would make a significant difference.
Fortunately we can 'dma' most of the data we need to transfer.

I've traced writes before, they are a lot faster and are limited
by things in the fpga fabric (they appear back to back).

	David