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Date: Tue, 7 Aug 2018 18:32:01 +0100
From: Ben Whitten <ben.whitten@...il.com>
To: afaerber@...e.de, starnight@...cu.edu.tw, hasnain.virk@....com
Cc: netdev@...r.kernel.org, Ben Whitten <ben.whitten@...rdtech.com>
Subject: [PATCH lora-next 01/10] net: lora: sx1301: add register, bit-fields, and helpers for regmap
From: Ben Whitten <ben.whitten@...rdtech.com>
The register and bit-field definitions are taken from the SX1301
datasheet version 2.01 dated June 2014 with the revision information
'First released version'.
The reset state and RW capability of each field is not reflected in this
patch however from the datasheet:
"Bits and registers that are not documented are reserved. They may
include calibration values. It is important not to modify these bits and
registers. If specific bits must be changed in a register with reserved
bits, the register must be read first, specific bits modified while
masking reserved bits and then the register can be written."
Then goes on to state:
"Reserved bits should be written with their reset state, they may be
read different states."
Caching is currently disabled.
The version is read back using regmap_read to verify regmap operation,
in doing so needs to be moved after priv and regmap allocation.
Signed-off-by: Ben Whitten <ben.whitten@...rdtech.com>
---
drivers/net/lora/Kconfig | 1 +
drivers/net/lora/sx1301.c | 282 +++++++++++++++++++++++++++++++++++++++++++---
drivers/net/lora/sx1301.h | 169 +++++++++++++++++++++++++++
3 files changed, 439 insertions(+), 13 deletions(-)
create mode 100644 drivers/net/lora/sx1301.h
diff --git a/drivers/net/lora/Kconfig b/drivers/net/lora/Kconfig
index bb57a01..79d23f2 100644
--- a/drivers/net/lora/Kconfig
+++ b/drivers/net/lora/Kconfig
@@ -49,6 +49,7 @@ config LORA_SX1301
tristate "Semtech SX1301 SPI driver"
default y
depends on SPI
+ select REGMAP_SPI
help
Semtech SX1301
diff --git a/drivers/net/lora/sx1301.c b/drivers/net/lora/sx1301.c
index 5342b61..49958f0 100644
--- a/drivers/net/lora/sx1301.c
+++ b/drivers/net/lora/sx1301.c
@@ -3,6 +3,7 @@
* Semtech SX1301 LoRa concentrator
*
* Copyright (c) 2018 Andreas Färber
+ * Copyright (c) 2018 Ben Whitten
*
* Based on SX1301 HAL code:
* Copyright (c) 2013 Semtech-Cycleo
@@ -19,6 +20,9 @@
#include <linux/of_gpio.h>
#include <linux/lora/dev.h>
#include <linux/spi/spi.h>
+#include <linux/regmap.h>
+
+#include "sx1301.h"
#define REG_PAGE_RESET 0
#define REG_VERSION 1
@@ -65,6 +69,213 @@
#define REG_EMERGENCY_FORCE_HOST_CTRL BIT(0)
+enum sx1301_fields {
+ F_SOFT_RESET,
+ F_START_BIST0,
+ F_START_BIST1,
+ F_BIST0_FINISHED,
+ F_BIST1_FINISHED,
+ F_GLOBAL_EN,
+ F_CLK32M_EN,
+ F_RADIO_A_EN,
+ F_RADIO_B_EN,
+ F_RADIO_RST,
+
+ F_RX_INVERT_IQ,
+ F_MODEM_INVERT_IQ,
+ F_MBWSSF_MODEM_INVERT_IQ,
+ F_RX_EDGE_SELECT,
+ F_MISC_RADIO_EN,
+ F_FSK_MODEM_INVERT_IQ,
+
+ F_RSSI_BB_FILTER_ALPHA,
+ F_RSSI_DEC_FILTER_ALPHA,
+ F_RSSI_CHANN_FILTER_ALPHA,
+
+ F_DEC_GAIN_OFFSET,
+ F_CHAN_GAIN_OFFSET,
+
+ F_LLR_SCALE,
+ F_SNR_AVG_CST,
+
+ F_CORR_NUM_SAME_PEAK,
+ F_CORR_MAC_GAIN,
+
+ F_FSK_CH_BW_EXPO,
+ F_FSK_RSSI_LENGTH,
+ F_FSK_RX_INVERT,
+ F_FSK_PKT_MODE,
+
+ F_FSK_PSIZE,
+ F_FSK_CRC_EN,
+ F_FSK_DCFREE_ENC,
+ F_FSK_CRC_IBM,
+
+ F_FSK_ERROR_OSR_TOL,
+ F_FSK_RADIO_SELECT,
+
+ F_TX_MODE,
+ F_TX_ZERO_PAD,
+ F_TX_EDGE_SELECT,
+ F_TX_EDGE_SELECT_TOP,
+
+ F_TX_GAIN,
+ F_TX_CHIRP_LOW_PASS,
+ F_TX_FCC_WIDEBAND,
+ F_TX_SWAP_IQ,
+
+ F_FSK_TX_GAUSSIAN_EN,
+ F_FSK_TX_GAUSSIAN_SELECT_BT,
+ F_FSK_TX_PATTERN_EN,
+ F_FSK_TX_PREAMBLE_SEQ,
+ F_FSK_TX_PSIZE,
+
+ F_FORCE_HOST_RADIO_CTRL,
+ F_FORCE_HOST_FE_CTRL,
+ F_FORCE_DEC_FILTER_GAIN,
+
+ F_MCU_RST_0,
+ F_MCU_RST_1,
+ F_MCU_SELECT_MUX_0,
+ F_MCU_SELECT_MUX_1,
+ F_MCU_CORRUPTION_DETECTED_0,
+ F_MCU_CORRUPTION_DETECTED_1,
+ F_MCU_SELECT_EDGE_0,
+ F_MCU_SELECT_EDGE_1,
+
+ F_EMERGENCY_FORCE_HOST_CTRL,
+};
+
+static const struct reg_field sx1301_reg_fields[] = {
+ /* PAGE */
+ [F_SOFT_RESET] = REG_FIELD(SX1301_PAGE, 7, 7),
+ /* BIST */
+ [F_START_BIST0] = REG_FIELD(SX1301_BIST, 0, 0),
+ [F_START_BIST1] = REG_FIELD(SX1301_BIST, 1, 1),
+ /* BIST_S */
+ [F_BIST0_FINISHED] = REG_FIELD(SX1301_BIST_S, 0, 0),
+ [F_BIST1_FINISHED] = REG_FIELD(SX1301_BIST_S, 1, 1),
+ /* GEN */
+ [F_GLOBAL_EN] = REG_FIELD(SX1301_GEN, 3, 3),
+ /* CKEN */
+ [F_CLK32M_EN] = REG_FIELD(SX1301_CKEN, 0, 0),
+ /* RADIO_CFG */
+ [F_RADIO_A_EN] = REG_FIELD(SX1301_RADIO_CFG, 0, 0),
+ [F_RADIO_B_EN] = REG_FIELD(SX1301_RADIO_CFG, 1, 1),
+ [F_RADIO_RST] = REG_FIELD(SX1301_RADIO_CFG, 2, 2),
+
+ /* IQCFG */
+ [F_RX_INVERT_IQ] = REG_FIELD(SX1301_IQCFG, 0, 0),
+ [F_MODEM_INVERT_IQ] = REG_FIELD(SX1301_IQCFG, 1, 1),
+ [F_MBWSSF_MODEM_INVERT_IQ] = REG_FIELD(SX1301_IQCFG, 2, 2),
+ [F_RX_EDGE_SELECT] = REG_FIELD(SX1301_IQCFG, 3, 3),
+ [F_MISC_RADIO_EN] = REG_FIELD(SX1301_IQCFG, 4, 4),
+ [F_FSK_MODEM_INVERT_IQ] = REG_FIELD(SX1301_IQCFG, 5, 5),
+
+ /* RSSI_X_FILTER_ALPHA */
+ [F_RSSI_BB_FILTER_ALPHA] =
+ REG_FIELD(SX1301_RSSI_BB_FILTER_ALPHA, 0, 4),
+ [F_RSSI_DEC_FILTER_ALPHA] =
+ REG_FIELD(SX1301_RSSI_DEC_FILTER_ALPHA, 0, 4),
+ [F_RSSI_CHANN_FILTER_ALPHA] =
+ REG_FIELD(SX1301_RSSI_CHANN_FILTER_ALPHA, 0, 4),
+
+ /* GAIN_OFFSET */
+ [F_DEC_GAIN_OFFSET] = REG_FIELD(SX1301_GAIN_OFFSET, 0, 3),
+ [F_CHAN_GAIN_OFFSET] = REG_FIELD(SX1301_GAIN_OFFSET, 4, 7),
+
+ /* MISC_CFG1 */
+ [F_LLR_SCALE] = REG_FIELD(SX1301_MISC_CFG1, 0, 3),
+ [F_SNR_AVG_CST] = REG_FIELD(SX1301_MISC_CFG1, 4, 5),
+
+ /* CORR_CFG */
+ [F_CORR_NUM_SAME_PEAK] = REG_FIELD(SX1301_CORR_CFG, 0, 3),
+ [F_CORR_MAC_GAIN] = REG_FIELD(SX1301_CORR_CFG, 4, 6),
+
+ /* FSK_CFG1 */
+ [F_FSK_CH_BW_EXPO] = REG_FIELD(SX1301_FSK_CFG1, 0, 2),
+ [F_FSK_RSSI_LENGTH] = REG_FIELD(SX1301_FSK_CFG1, 3, 5),
+ [F_FSK_RX_INVERT] = REG_FIELD(SX1301_FSK_CFG1, 6, 6),
+ [F_FSK_PKT_MODE] = REG_FIELD(SX1301_FSK_CFG1, 7, 7),
+
+ /* FSK_CFG2 */
+ [F_FSK_PSIZE] = REG_FIELD(SX1301_FSK_CFG2, 0, 2),
+ [F_FSK_CRC_EN] = REG_FIELD(SX1301_FSK_CFG2, 3, 3),
+ [F_FSK_DCFREE_ENC] = REG_FIELD(SX1301_FSK_CFG2, 4, 5),
+ [F_FSK_CRC_IBM] = REG_FIELD(SX1301_FSK_CFG2, 6, 6),
+
+ /* FSK_ERROR_OSR_TOL */
+ [F_FSK_ERROR_OSR_TOL] = REG_FIELD(SX1301_FSK_ERROR_OSR_TOL, 0, 4),
+ [F_FSK_RADIO_SELECT] = REG_FIELD(SX1301_FSK_ERROR_OSR_TOL, 7, 7),
+
+ /* TX_CFG1 */
+ [F_TX_MODE] = REG_FIELD(SX1301_TX_CFG1, 0, 0),
+ [F_TX_ZERO_PAD] = REG_FIELD(SX1301_TX_CFG1, 1, 4),
+ [F_TX_EDGE_SELECT] = REG_FIELD(SX1301_TX_CFG1, 5, 5),
+ [F_TX_EDGE_SELECT_TOP] = REG_FIELD(SX1301_TX_CFG1, 6, 6),
+
+ /* TX_CFG2 */
+ [F_TX_GAIN] = REG_FIELD(SX1301_TX_CFG2, 0, 1),
+ [F_TX_CHIRP_LOW_PASS] = REG_FIELD(SX1301_TX_CFG2, 2, 4),
+ [F_TX_FCC_WIDEBAND] = REG_FIELD(SX1301_TX_CFG2, 5, 6),
+ [F_TX_SWAP_IQ] = REG_FIELD(SX1301_TX_CFG2, 7, 7),
+
+ /* FSK_TX */
+ [F_FSK_TX_GAUSSIAN_EN] = REG_FIELD(SX1301_FSK_TX, 0, 0),
+ [F_FSK_TX_GAUSSIAN_SELECT_BT] = REG_FIELD(SX1301_FSK_TX, 1, 2),
+ [F_FSK_TX_PATTERN_EN] = REG_FIELD(SX1301_FSK_TX, 3, 3),
+ [F_FSK_TX_PREAMBLE_SEQ] = REG_FIELD(SX1301_FSK_TX, 4, 4),
+ [F_FSK_TX_PSIZE] = REG_FIELD(SX1301_FSK_TX, 5, 7),
+
+ /* FORCE_CTRL */
+ [F_FORCE_HOST_RADIO_CTRL] = REG_FIELD(SX1301_FORCE_CTRL, 1, 1),
+ [F_FORCE_HOST_FE_CTRL] = REG_FIELD(SX1301_FORCE_CTRL, 2, 2),
+ [F_FORCE_DEC_FILTER_GAIN] = REG_FIELD(SX1301_FORCE_CTRL, 3, 3),
+
+ /* MCU_CTRL */
+ [F_MCU_RST_0] = REG_FIELD(SX1301_MCU_CTRL, 0, 0),
+ [F_MCU_RST_1] = REG_FIELD(SX1301_MCU_CTRL, 1, 1),
+ [F_MCU_SELECT_MUX_0] = REG_FIELD(SX1301_MCU_CTRL, 2, 2),
+ [F_MCU_SELECT_MUX_1] = REG_FIELD(SX1301_MCU_CTRL, 3, 3),
+ [F_MCU_CORRUPTION_DETECTED_0] = REG_FIELD(SX1301_MCU_CTRL, 4, 4),
+ [F_MCU_CORRUPTION_DETECTED_1] = REG_FIELD(SX1301_MCU_CTRL, 5, 5),
+ [F_MCU_SELECT_EDGE_0] = REG_FIELD(SX1301_MCU_CTRL, 6, 6),
+ [F_MCU_SELECT_EDGE_1] = REG_FIELD(SX1301_MCU_CTRL, 7, 7),
+
+ /* EMERGENCY_FORCE_HOST_CTRL */
+ [F_EMERGENCY_FORCE_HOST_CTRL] =
+ REG_FIELD(SX1301_EMERGENCY_FORCE_HOST_CTRL, 0, 0),
+};
+
+static const struct regmap_range_cfg sx1301_ranges[] = {
+ {
+ .name = "Pages",
+
+ .range_min = SX1301_VIRT_BASE,
+ .range_max = SX1301_MAX_REGISTER,
+
+ .selector_reg = SX1301_PAGE,
+ .selector_mask = 0x3,
+
+ .window_start = 0,
+ .window_len = SX1301_PAGE_LEN,
+ },
+};
+
+static struct regmap_config sx1301_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .cache_type = REGCACHE_NONE,
+
+ .read_flag_mask = 0,
+ .write_flag_mask = BIT(7),
+
+ .ranges = sx1301_ranges,
+ .num_ranges = ARRAY_SIZE(sx1301_ranges),
+ .max_register = SX1301_MAX_REGISTER,
+};
+
struct spi_sx1301 {
struct spi_device *parent;
u8 page;
@@ -76,8 +287,29 @@ struct sx1301_priv {
struct gpio_desc *rst_gpio;
u8 cur_page;
struct spi_controller *radio_a_ctrl, *radio_b_ctrl;
+ struct regmap *regmap;
+ struct regmap_field *regmap_fields[ARRAY_SIZE(sx1301_reg_fields)];
};
+static int sx1301_field_read(struct sx1301_priv *priv,
+ enum sx1301_fields field_id)
+{
+ int ret;
+ int val;
+
+ ret = regmap_field_read(priv->regmap_fields[field_id], &val);
+ if (ret)
+ return ret;
+
+ return val;
+}
+
+static int sx1301_field_write(struct sx1301_priv *priv,
+ enum sx1301_fields field_id, u8 val)
+{
+ return regmap_field_write(priv->regmap_fields[field_id], val);
+}
+
static int sx1301_read_burst(struct spi_device *spi, u8 reg, u8 *val, size_t len)
{
u8 addr = reg & 0x7f;
@@ -620,6 +852,8 @@ static int sx1301_probe(struct spi_device *spi)
struct spi_sx1301 *radio;
struct gpio_desc *rst;
int ret;
+ int i;
+ unsigned int ver;
u8 val;
rst = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_LOW);
@@ -634,18 +868,6 @@ static int sx1301_probe(struct spi_device *spi)
spi->bits_per_word = 8;
spi_setup(spi);
- ret = sx1301_read(spi, REG_VERSION, &val);
- if (ret) {
- dev_err(&spi->dev, "version read failed\n");
- goto err_version;
- }
-
- if (val != 103) {
- dev_err(&spi->dev, "unexpected version: %u\n", val);
- ret = -ENXIO;
- goto err_version;
- }
-
netdev = alloc_loradev(sizeof(*priv));
if (!netdev) {
ret = -ENOMEM;
@@ -659,6 +881,38 @@ static int sx1301_probe(struct spi_device *spi)
spi_set_drvdata(spi, netdev);
SET_NETDEV_DEV(netdev, &spi->dev);
+ priv->regmap = devm_regmap_init_spi(spi, &sx1301_regmap_config);
+ if (IS_ERR(priv->regmap)) {
+ ret = PTR_ERR(priv->regmap);
+ dev_err(&spi->dev, "Regmap allocation failed: %d\n", ret);
+ return err_regmap;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sx1301_reg_fields); i++) {
+ const struct reg_field *reg_fields = sx1301_reg_fields;
+
+ priv->regmap_fields[i] = devm_regmap_field_alloc(&spi->dev,
+ priv->regmap,
+ reg_fields[i]);
+ if (IS_ERR(priv->regmap_fields[i])) {
+ ret = PTR_ERR(priv->regmap_fields[i]);
+ dev_err(&spi->dev, "Cannot allocate regmap field: %d\n", ret);
+ goto err_regmap;
+ }
+ }
+
+ ret = regmap_read(priv->regmap, SX1301_VER, &ver);
+ if (ret) {
+ dev_err(&spi->dev, "version read failed\n");
+ goto err_version;
+ }
+
+ if (ver != 103) {
+ dev_err(&spi->dev, "unexpected version: %u\n", ver);
+ ret = -ENXIO;
+ goto err_version;
+ }
+
ret = sx1301_write(spi, REG_PAGE_RESET, 0);
if (ret) {
dev_err(&spi->dev, "page/reset write failed\n");
@@ -888,9 +1142,10 @@ static int sx1301_probe(struct spi_device *spi)
err_read_global_en_0:
err_soft_reset:
err_init_page:
+err_version:
+err_regmap:
free_loradev(netdev);
err_alloc_loradev:
-err_version:
return ret;
}
@@ -927,4 +1182,5 @@ module_spi_driver(sx1301_spi_driver);
MODULE_DESCRIPTION("SX1301 SPI driver");
MODULE_AUTHOR("Andreas Färber <afaerber@...e.de>");
+MODULE_AUTHOR("Ben Whitten <ben.whitten@...il.com>");
MODULE_LICENSE("GPL");
diff --git a/drivers/net/lora/sx1301.h b/drivers/net/lora/sx1301.h
new file mode 100644
index 0000000..abfb7b5
--- /dev/null
+++ b/drivers/net/lora/sx1301.h
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Semtech SX1301 lora concentrator
+ *
+ * Copyright (c) 2018 Ben Whitten
+ */
+
+#ifndef _SX1301_
+#define _SX1301_
+
+/* Page independent */
+#define SX1301_PAGE 0x00
+#define SX1301_VER 0x01
+#define SX1301_RDBAL 0x02
+#define SX1301_RDBAH 0x03
+#define SX1301_RDBD 0x04
+#define SX1301_TDBA 0x05
+#define SX1301_TDBD 0x06
+#define SX1301_MPA 0x09
+#define SX1301_MPD 0x0A
+#define SX1301_RPNS 0x0B
+#define SX1301_RPAPL 0x0C
+#define SX1301_RPAPH 0x0D
+#define SX1301_RPS 0x0E
+#define SX1301_RPPS 0x0F
+#define SX1301_GEN 0x10
+#define SX1301_CKEN 0x11
+#define SX1301_BIST 0x12
+#define SX1301_BIST_S 0x13
+#define SX1301_GPSI 0x1B
+#define SX1301_GPSO 0x1C
+#define SX1301_GPMODE 0x1D
+#define SX1301_GPREGI 0x1E
+#define SX1301_GPREGO 0x1F
+#define SX1301_AGCSTS 0x20
+#define SX1301_ARBSTS 0x7D
+#define SX1301_ID 0x7F
+
+#define SX1301_VIRT_BASE 0x100
+#define SX1301_PAGE_LEN 0x80
+#define SX1301_PAGE_BASE(n) (SX1301_VIRT_BASE + (SX1301_PAGE_LEN * n))
+
+/* Page 0 */
+#define SX1301_IQCFG (SX1301_PAGE_BASE(0) + 0x21)
+#define SX1301_DECCFG (SX1301_PAGE_BASE(0) + 0x22)
+#define SX1301_CHRS (SX1301_PAGE_BASE(0) + 0x23)
+#define SX1301_IF0L (SX1301_PAGE_BASE(0) + 0x24)
+#define SX1301_IF0H (SX1301_PAGE_BASE(0) + 0x25)
+#define SX1301_IF1L (SX1301_PAGE_BASE(0) + 0x26)
+#define SX1301_IF1H (SX1301_PAGE_BASE(0) + 0x27)
+#define SX1301_IF2L (SX1301_PAGE_BASE(0) + 0x28)
+#define SX1301_IF2H (SX1301_PAGE_BASE(0) + 0x29)
+#define SX1301_IF3L (SX1301_PAGE_BASE(0) + 0x2A)
+#define SX1301_IF3H (SX1301_PAGE_BASE(0) + 0x2B)
+#define SX1301_IF4L (SX1301_PAGE_BASE(0) + 0x2C)
+#define SX1301_IF4H (SX1301_PAGE_BASE(0) + 0x2D)
+#define SX1301_IF5L (SX1301_PAGE_BASE(0) + 0x2E)
+#define SX1301_IF5H (SX1301_PAGE_BASE(0) + 0x2F)
+#define SX1301_IF6L (SX1301_PAGE_BASE(0) + 0x30)
+#define SX1301_IF6H (SX1301_PAGE_BASE(0) + 0x31)
+#define SX1301_IF7L (SX1301_PAGE_BASE(0) + 0x32)
+#define SX1301_IF7H (SX1301_PAGE_BASE(0) + 0x33)
+#define SX1301_IF8L (SX1301_PAGE_BASE(0) + 0x34)
+#define SX1301_IF8H (SX1301_PAGE_BASE(0) + 0x35)
+#define SX1301_IF9L (SX1301_PAGE_BASE(0) + 0x36)
+#define SX1301_IF9H (SX1301_PAGE_BASE(0) + 0x37)
+#define SX1301_COR0DETEN (SX1301_PAGE_BASE(0) + 0x41)
+#define SX1301_COR1DETEN (SX1301_PAGE_BASE(0) + 0x42)
+#define SX1301_COR2DETEN (SX1301_PAGE_BASE(0) + 0x43)
+#define SX1301_COR3DETEN (SX1301_PAGE_BASE(0) + 0x44)
+#define SX1301_COR4DETEN (SX1301_PAGE_BASE(0) + 0x45)
+#define SX1301_COR5DETEN (SX1301_PAGE_BASE(0) + 0x46)
+#define SX1301_COR6DETEN (SX1301_PAGE_BASE(0) + 0x47)
+#define SX1301_COR7DETEN (SX1301_PAGE_BASE(0) + 0x48)
+#define SX1301_CORR_CFG (SX1301_PAGE_BASE(0) + 0x4E)
+#define SX1301_MODEM_START_RDX4_L (SX1301_PAGE_BASE(0) + 0x51)
+#define SX1301_MODEM_START_RDX4_H (SX1301_PAGE_BASE(0) + 0x52)
+#define SX1301_MODEM_START_SF12_RDX4_L (SX1301_PAGE_BASE(0) + 0x53)
+#define SX1301_MODEM_START_SF12_RDX4_H (SX1301_PAGE_BASE(0) + 0x54)
+#define SX1301_TIMTRAK2 (SX1301_PAGE_BASE(0) + 0x5D)
+#define SX1301_PRSYMBNBL (SX1301_PAGE_BASE(0) + 0x60)
+#define SX1301_PRSYMBNBH (SX1301_PAGE_BASE(0) + 0x61)
+#define SX1301_MISC_CFG1 (SX1301_PAGE_BASE(0) + 0x63)
+#define SX1301_MISC_CFG2 (SX1301_PAGE_BASE(0) + 0x64)
+#define SX1301_HEADER_CFG1 (SX1301_PAGE_BASE(0) + 0x65)
+#define SX1301_HEADER_CFG2 (SX1301_PAGE_BASE(0) + 0x66)
+#define SX1301_GAIN_OFFSET (SX1301_PAGE_BASE(0) + 0x68)
+#define SX1301_FORCE_CTRL (SX1301_PAGE_BASE(0) + 0x69)
+#define SX1301_MCU_CTRL (SX1301_PAGE_BASE(0) + 0x6A)
+#define SX1301_CHANN_SELECT_RSSI (SX1301_PAGE_BASE(0) + 0x6B)
+#define SX1301_RSSI_BB_DEFAULT_VALUE (SX1301_PAGE_BASE(0) + 0x6C)
+#define SX1301_RSSI_DEC_DEFAULT_VALUE (SX1301_PAGE_BASE(0) + 0x6D)
+#define SX1301_RSSI_CHANN_DEFAULT_VALUE (SX1301_PAGE_BASE(0) + 0x6E)
+#define SX1301_RSSI_BB_FILTER_ALPHA (SX1301_PAGE_BASE(0) + 0x6F)
+#define SX1301_RSSI_DEC_FILTER_ALPHA (SX1301_PAGE_BASE(0) + 0x70)
+#define SX1301_RSSI_CHANN_FILTER_ALPHA (SX1301_PAGE_BASE(0) + 0x71)
+
+/* Page 1 */
+#define SX1301_TXTRIG (SX1301_PAGE_BASE(1) + 0x21)
+#define SX1301_TX_OFFSET_I (SX1301_PAGE_BASE(1) + 0x27)
+#define SX1301_TX_OFFSET_Q (SX1301_PAGE_BASE(1) + 0x28)
+#define SX1301_TX_CFG1 (SX1301_PAGE_BASE(1) + 0x29)
+#define SX1301_TX_CFG2 (SX1301_PAGE_BASE(1) + 0x2A)
+#define SX1301_BHIMPCFG1 (SX1301_PAGE_BASE(1) + 0x2B)
+#define SX1301_BHIMPCFG2 (SX1301_PAGE_BASE(1) + 0x2C)
+#define SX1301_BHSYNCPOS (SX1301_PAGE_BASE(1) + 0x2E)
+#define SX1301_BHPRSYMNBL (SX1301_PAGE_BASE(1) + 0x2F)
+#define SX1301_MBWSSF_MISC_CFG1 (SX1301_PAGE_BASE(1) + 0x3A)
+#define SX1301_MBWSSF_MISC_CFG2 (SX1301_PAGE_BASE(1) + 0x3B)
+#define SX1301_MBWSSF_MISC_CFG3 (SX1301_PAGE_BASE(1) + 0x3C)
+#define SX1301_MBWSSF_MISC_CFG4 (SX1301_PAGE_BASE(1) + 0x3D)
+#define SX1301_TX_STATUS (SX1301_PAGE_BASE(1) + 0x3E)
+#define SX1301_FSK_CFG1 (SX1301_PAGE_BASE(1) + 0x3F)
+#define SX1301_FSK_CFG2 (SX1301_PAGE_BASE(1) + 0x40)
+#define SX1301_FSK_ERROR_OSR_TOL (SX1301_PAGE_BASE(1) + 0x41)
+#define SX1301_FSK_BR_RATIOL (SX1301_PAGE_BASE(1) + 0x42)
+#define SX1301_FSK_BR_RATIOH (SX1301_PAGE_BASE(1) + 0x43)
+#define SX1301_FSK_REF_PATTERN_0 (SX1301_PAGE_BASE(1) + 0x44)
+#define SX1301_FSK_REF_PATTERN_1 (SX1301_PAGE_BASE(1) + 0x45)
+#define SX1301_FSK_REF_PATTERN_2 (SX1301_PAGE_BASE(1) + 0x46)
+#define SX1301_FSK_REF_PATTERN_3 (SX1301_PAGE_BASE(1) + 0x47)
+#define SX1301_FSK_REF_PATTERN_4 (SX1301_PAGE_BASE(1) + 0x48)
+#define SX1301_FSK_REF_PATTERN_5 (SX1301_PAGE_BASE(1) + 0x49)
+#define SX1301_FSK_REF_PATTERN_6 (SX1301_PAGE_BASE(1) + 0x4A)
+#define SX1301_FSK_REF_PATTERN_7 (SX1301_PAGE_BASE(1) + 0x4B)
+#define SX1301_FSK_PKT_LENGTH (SX1301_PAGE_BASE(1) + 0x4C)
+#define SX1301_FSK_TX (SX1301_PAGE_BASE(1) + 0x4D)
+#define SX1301_FSK_AAFC (SX1301_PAGE_BASE(1) + 0x52)
+#define SX1301_FSK_PATTERN_TIMEOUT_CFGL (SX1301_PAGE_BASE(1) + 0x53)
+#define SX1301_FSK_PATTERN_TIMEOUT_CFGH (SX1301_PAGE_BASE(1) + 0x54)
+
+/* Page 2 */
+#define SX1301_RADIO_A_SPI_DATA (SX1301_PAGE_BASE(2) + 0x21)
+#define SX1301_RADIO_A_SPI_DATA_RB (SX1301_PAGE_BASE(2) + 0x22)
+#define SX1301_RADIO_A_SPI_ADDR (SX1301_PAGE_BASE(2) + 0x23)
+#define SX1301_RADIO_A_SPI_CS (SX1301_PAGE_BASE(2) + 0x25)
+#define SX1301_RADIO_B_SPI_DATA (SX1301_PAGE_BASE(2) + 0x26)
+#define SX1301_RADIO_B_SPI_DATA_RB (SX1301_PAGE_BASE(2) + 0x27)
+#define SX1301_RADIO_B_SPI_ADDR (SX1301_PAGE_BASE(2) + 0x28)
+#define SX1301_RADIO_B_SPI_CS (SX1301_PAGE_BASE(2) + 0x2A)
+#define SX1301_RADIO_CFG (SX1301_PAGE_BASE(2) + 0x2B)
+#define SX1301_PA_GAIN (SX1301_PAGE_BASE(2) + 0x2C)
+#define SX1301_FE_A_CTRL_LUT (SX1301_PAGE_BASE(2) + 0x2D)
+#define SX1301_FE_B_CTRL_LUT (SX1301_PAGE_BASE(2) + 0x2E)
+#define SX1301_VALID_HEADER_COUNTER_M_WSSF (SX1301_PAGE_BASE(2) + 0x38)
+#define SX1301_VALID_HEADER_COUNTER_FSK (SX1301_PAGE_BASE(2) + 0x39)
+#define SX1301_VALID_PACKET_COUNTER_MB_SSF (SX1301_PAGE_BASE(2) + 0x3A)
+#define SX1301_VALID_PACKET_COUNTER_FSK (SX1301_PAGE_BASE(2) + 0x3B)
+#define SX1301_CHANN_RSSI (SX1301_PAGE_BASE(2) + 0x3C)
+#define SX1301_BB_RSSI (SX1301_PAGE_BASE(2) + 0x3D)
+#define SX1301_DEC_RSSI (SX1301_PAGE_BASE(2) + 0x3E)
+#define SX1301_DBG_MCU_DATA (SX1301_PAGE_BASE(2) + 0x3F)
+#define SX1301_DBG_ARB_MCU_RAM_DATA (SX1301_PAGE_BASE(2) + 0x40)
+#define SX1301_DBG_AGC_MCU_RAM_DATA (SX1301_PAGE_BASE(2) + 0x41)
+#define SX1301_TIMESTAMP_0 (SX1301_PAGE_BASE(2) + 0x46)
+#define SX1301_TIMESTAMP_1 (SX1301_PAGE_BASE(2) + 0x47)
+#define SX1301_TIMESTAMP_2 (SX1301_PAGE_BASE(2) + 0x48)
+#define SX1301_TIMESTAMP_3 (SX1301_PAGE_BASE(2) + 0x49)
+#define SX1301_DBG_ARB_MCU_RAM_ADDR (SX1301_PAGE_BASE(2) + 0x50)
+#define SX1301_DBG_AGC_MCU_RAM_ADDR (SX1301_PAGE_BASE(2) + 0x51)
+#define SX1301_SPI_MASTER_CFG (SX1301_PAGE_BASE(2) + 0x52)
+#define SX1301_GPS_CFG (SX1301_PAGE_BASE(2) + 0x59)
+
+/* Page 3 */
+#define SX1301_EMERGENCY_FORCE_HOST_CTRL (SX1301_PAGE_BASE(3) + 0x7F)
+
+#define SX1301_MAX_REGISTER (SX1301_PAGE_BASE(3) + 0x7F)
+
+#endif
--
2.7.4
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