netdev - Re: [PATCH 2/2] net: dsa: mv88e6xxx: Handle single-chip-address OF property

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Date:   Sat, 23 Apr 2022 17:18:57 +0200
From:   Marek Behún <kabel@...nel.org>
To:     Nathan Rossi <nathan@...hanrossi.com>
Cc:     Andrew Lunn <andrew@...n.ch>, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>
Subject: Re: [PATCH 2/2] net: dsa: mv88e6xxx: Handle single-chip-address OF
 property

On Sun, 24 Apr 2022 00:41:22 +1000
Nathan Rossi <nathan@...hanrossi.com> wrote:

> On Sun, 24 Apr 2022 at 00:07, Andrew Lunn <andrew@...n.ch> wrote:
> >
> > On Sat, Apr 23, 2022 at 01:14:27PM +0000, Nathan Rossi wrote:  
> > > Handle the parsing and use of single chip addressing when the switch has
> > > the single-chip-address property defined. This allows for specifying the
> > > switch as using single chip addressing even when mdio address 0 is used
> > > by another device on the bus. This is a feature of some switches (e.g.
> > > the MV88E6341/MV88E6141) where the switch shares the bus only responding
> > > to the higher 16 addresses.  
> >
> > Hi Nathan
> >
> > I think i'm missing something in this explanation:
> >
> > smi.c says:
> >
> > /* The switch ADDR[4:1] configuration pins define the chip SMI device address
> >  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
> >  *
> >  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
> >  * is the only device connected to the SMI master. In this mode it responds to
> >  * all 32 possible SMI addresses, and thus maps directly the internal devices.
> >  *
> >  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
> >  * multiple devices to share the SMI interface. In this mode it responds to only
> >  * 2 registers, used to indirectly access the internal SMI devices.
> >  *
> >  * Some chips use a different scheme: Only the ADDR4 pin is used for
> >  * configuration, and the device responds to 16 of the 32 SMI
> >  * addresses, allowing two to coexist on the same SMI interface.
> >  */
> >
> > So if ADDR = 0, it takes up the whole bus. And in this case reg = 0.
> > If ADDR != 0, it is in multi chip mode, and DT reg = ADDR.
> >
> > int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
> >                        struct mii_bus *bus, int sw_addr)
> > {
> >         if (chip->info->dual_chip)
> >                 chip->smi_ops = &mv88e6xxx_smi_dual_direct_ops;
> >         else if (sw_addr == 0)
> >                 chip->smi_ops = &mv88e6xxx_smi_direct_ops;
> >         else if (chip->info->multi_chip)
> >                 chip->smi_ops = &mv88e6xxx_smi_indirect_ops;
> >         else
> >                 return -EINVAL;
> >
> > This seems to implement what is above. smi_direct_ops == whole bus,
> > smi_indirect_ops == multi-chip mode.
> >
> > In what situation do you see this not working? What device are you
> > using, what does you DT look like, and what at the ADDR value?  
> 
> The device I am using is the MV88E6141, it follows the second scheme
> such that it only responds to the upper 16 of the 32 SMI addresses in
> single chip addressing mode. I am able to define the switch at address
> 0, and everything works. However in the device I am using (Netgate
> SG-3100) the ethernet phys for the non switch ethernet interfaces are
> also on the same mdio bus as the switch. One of those phys is
> configured with address 0. Defining both the ethernet-phy and switch
> as address 0 does not work.

This makes the need of new property reasonable. You can add my

Acked-by: Marek Behún <kabel@...nel.org>