lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date: Thu, 18 May 2023 08:51:10 +0000
From: "Gaddam, Sarath Babu Naidu" <sarath.babu.naidu.gaddam@....com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
	"davem@...emloft.net" <davem@...emloft.net>, "edumazet@...gle.com"
	<edumazet@...gle.com>, "kuba@...nel.org" <kuba@...nel.org>,
	"pabeni@...hat.com" <pabeni@...hat.com>, "robh+dt@...nel.org"
	<robh+dt@...nel.org>, "krzysztof.kozlowski+dt@...aro.org"
	<krzysztof.kozlowski+dt@...aro.org>
CC: "linux@...linux.org.uk" <linux@...linux.org.uk>, "Simek, Michal"
	<michal.simek@....com>, "Pandey, Radhey Shyam" <radhey.shyam.pandey@....com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "Sarangi, Anirudha"
	<anirudha.sarangi@....com>, "Katakam, Harini" <harini.katakam@....com>, "git
 (AMD-Xilinx)" <git@....com>
Subject: RE: [PATCH net-next V3 1/3] dt-bindings: net: xilinx_axienet:
 Introduce dmaengine binding support



> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Sent: Wednesday, May 17, 2023 8:19 PM
> To: Gaddam, Sarath Babu Naidu
> <sarath.babu.naidu.gaddam@....com>; davem@...emloft.net;
> edumazet@...gle.com; kuba@...nel.org; pabeni@...hat.com;
> robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org
> Cc: linux@...linux.org.uk; Simek, Michal <michal.simek@....com>;
> Pandey, Radhey Shyam <radhey.shyam.pandey@....com>;
> netdev@...r.kernel.org; devicetree@...r.kernel.org; linux-arm-
> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org; Sarangi,
> Anirudha <anirudha.sarangi@....com>; Katakam, Harini
> <harini.katakam@....com>; git (AMD-Xilinx) <git@....com>
> Subject: Re: [PATCH net-next V3 1/3] dt-bindings: net: xilinx_axienet:
> Introduce dmaengine binding support
> 
> On 17/05/2023 14:06, Gaddam, Sarath Babu Naidu wrote:
> >>>>> +  dma-names:
> >>>>> +    items:
> >>>>> +      - const: tx_chan0
> >>>>
> >>>> tx
> >>>>
> >>>>> +      - const: rx_chan0
> >>>>
> >>>> rx
> >>>
> >>> We want to support more channels in the future, currently we
> support
> >>> AXI DMA which has only one tx and rx channel. In future we want to
> >>> extend support for multichannel DMA (MCDMA) which has 16 TX and
> >>> 16 RX channels. To uniquely identify each channel, we are using chan
> >>> suffix. Depending on the usecase AXI ethernet driver can request any
> >>> combination of multichannel DMA  channels.
> >>>
> >>> dma-names = tx_chan0, tx_chan1, rx_chan0, rx_chan1;
> >>>
> >>> will update the commit message with same.
> >>
> >> I expect the binding to be complete, otherwise you get comments like
> this.
> >> Add missing parts to the binding and resend.
> >
> > Binding is complete for current supported DMA (single channel).  We
> > will extend when we add MCDMA.
> 
> What doe sit mean "current supported DMA"? By driver? or by hardware?
> If the former, then how does it matter for the bindings?
> 
> If the latter, then your hardware is going to change? Then you will have
> different set of compatibles and then can use different names.
> 
> >
> > We will describe the reason for using channel suffix in the
> > description as below.
> >
> >    dma-names:
> >       items:
> >         - const: tx_chan0
> >         - const: rx_chan0
> >      description: |
> >            Chan suffix is used for identifying each channel uniquely.
> >            Current DMA has only one Tx and Rx channel but it will be
> >            extended to support for multichannel DMA (MCDMA) which
> >            has 16 TX and 16 RX channels. Depending on the usecase AXI
> >            ethernet driver can request any combination of multichannel
> >            DMA  channels.
> 
> No, because I don't understand what is "will be extended". Bindings
> should be complete. If they are going to be extended, it means they are
> not complete. If they cannot be complete, which happens, please provide
> a reason. There was no reason so far, except your claim it is complete.

We will re-spin another series with complete bindings including MCDMA
support.

Thanks,
Sarath

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ