netdev - Re: [PATCH net v2] net: phy: marvell10g: fix 88x3310 power up

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Date: Thu, 20 Jul 2023 13:34:25 +0200
From: Paolo Abeni <pabeni@...hat.com>
To: Jiawen Wu <jiawenwu@...stnetic.com>, linux@...linux.org.uk, 
 kabel@...nel.org, andrew@...n.ch, hkallweit1@...il.com,
 davem@...emloft.net,  edumazet@...gle.com, kuba@...nel.org,
 netdev@...r.kernel.org
Subject: Re: [PATCH net v2] net: phy: marvell10g: fix 88x3310 power up

On Wed, 2023-07-19 at 17:22 +0800, Jiawen Wu wrote:
> Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY,
> it sometimes does not take effect immediately. And a read of this
> register causes the bit not to clear. This will cause mv3310_reset()
> to time out, which will fail the config initialization. So add a delay
> before the next access.
> 
> Fixes: c9cc1c815d36 ("net: phy: marvell10g: place in powersave mode at probe")
> Signed-off-by: Jiawen Wu <jiawenwu@...stnetic.com>
> ---
> v1 -> v2:
> - change poll-bit-clear to time delay
> ---
>  drivers/net/phy/marvell10g.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
> index 55d9d7acc32e..d4bb90d76881 100644
> --- a/drivers/net/phy/marvell10g.c
> +++ b/drivers/net/phy/marvell10g.c
> @@ -328,6 +328,13 @@ static int mv3310_power_up(struct phy_device *phydev)
>  	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
>  				 MV_V2_PORT_CTRL_PWRDOWN);
>  
> +	/* Sometimes, the power down bit doesn't clear immediately, and
> +	 * a read of this register causes the bit not to clear. Delay
> +	 * 100us to allow the PHY to come out of power down mode before
> +	 * the next access.
> +	 */
> +	udelay(100);

Out of sheer ignorance, would an usleep_range(...) be more appropriate
here?

Thanks!

Paolo