netdev - Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties

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Date: Thu, 4 Jan 2024 17:53:10 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Andrew Lunn <andrew@...n.ch>
CC: Christian Marangi <ansuelsmth@...il.com>,
        "Russell King (Oracle)"
	<linux@...linux.org.uk>,
        <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
        <pabeni@...hat.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <hkallweit1@...il.com>, <corbet@....net>, <p.zabel@...gutronix.de>,
        <f.fainelli@...il.com>, <netdev@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-doc@...r.kernel.org>
Subject: Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY
 properties

On 1/3/2024 10:22 PM, Andrew Lunn wrote:
>> Yes, APQ8084 is the application SoC.
>> QCA8084 is the pure PHY chip which has quad-phy.
> 
> I think everybody agrees these are terrible names, being so close
> together but being very different devices.
> 
> You have the issues of not giving clear explanations of your
> hardware. This is resulting in a lot of wasted tome for everybody. S
> please make your explanations very clear. I personally would avoid
> using APQ8084 or QCA8084 on there own. Always say the application SoC
> APQ8084, or the PHY chip QCA8084, or the switch embedded within the
> application processor APQ8084, or the PHYs embedded within the
> Application processor etc. This is particularly important when talking
> about clocks and resets, since the PHYs embedded within the
> application processor are likely to have different clocks and reset
> controllers to the PHY chip QCA8084.
> 
> 	Andrew

Let me explain it more.
APQ8084 is the Snapdragon SoC(for smart phone or other applicaiton)
according to the link below.
https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-processors-805.
which has nothing to do with QCA8084 or IPQ SoC we are discussing here.
let's remove out the APQ SoC from the discussion here.

1. For IPQ SoC series, there are only ipq4019, ipq5018, ipq6018,
ipq8074 documented in the current dt-bindings doc qcom,ipq4019-mdio.yaml
and ipq9574, ipq5332 that are being added by the MDIO patch, and one
more ipq8064 whose MDIO driver is mdio-ipq8064.c, on more others.

2. For qca8084(pure PHY chip), which is the quad-phy chip, which is just
    like qca8081 PHY(single port PHY), each port can be linked to maximum
    speed 2.5G.

    For qca8386(switch chip), which includes the same PHY CHIP as qca8084
    (4 physical ports and two CPU ports), qca8386 switch can work with
    the current qca8k.c DSA driver with the supplement patches.

    Both qca8084 and qca8386 includes same network clock controller(let's
    call it NSSCC, since this clock controller is located in the
    Ethernet chip qca8084 and qca8386), they have the same clock initial
    configuration sequence to initialize the Ethernet chip.

   The Ethernet chip qca8084 and qca8386 are only connected with IPQ SoC,
   Currently qca8084 is connected with IPQ SoC by 10G-QXGMII mode.
   the 4 PHYs of qca8386 are connected with the internal MAC of qca8386
   by GMII, the maximum speed is also 2.5G.
   The port4 of qca8084 or qca8386 is optionally be able to connected
   with IPQ SoC by sgmii.