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Date: Thu, 28 Mar 2024 16:22:57 +0530
From: geethasowjanya <geethasowjanya.kornu@...il.com>
To: Karol Kolacinski <karol.kolacinski@...el.com>
Cc: intel-wired-lan@...ts.osuosl.org, netdev@...r.kernel.org,
anthony.l.nguyen@...el.com, jesse.brandeburg@...el.com,
Sergey Temerkhanov <sergey.temerkhanov@...el.com>,
Przemek Kitszel <przemyslaw.kitszel@...el.com>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
Subject: Re: [PATCH v2 iwl-next 03/12] ice: Implement Tx interrupt enablement functions
On Thu, Mar 28, 2024 at 3:04 PM Karol Kolacinski
<karol.kolacinski@...el.com> wrote:
>
> From: Sergey Temerkhanov <sergey.temerkhanov@...el.com>
>
> Introduce functions enabling/disabling Tx TS interrupts
> for the E822 and ETH56G PHYs
>
> Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@...el.com>
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@...el.com>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
> ---
> drivers/net/ethernet/intel/ice/ice_ptp.c | 63 ++++++++++-----------
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 31 ++++++++++
> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 +-
> 3 files changed, 63 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
> index 8150f949dfd3..3019988a43c8 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
> @@ -1457,42 +1457,43 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
> * @ena: bool value to enable or disable interrupt
> * @threshold: Minimum number of packets at which intr is triggered
> *
> - * Utility function to enable or disable Tx timestamp interrupt and threshold
> + * Utility function to configure all the PHY interrupt settings, including
> + * whether the PHY interrupt is enabled, and what threshold to use. Also
> + * configures The E82X timestamp owner to react to interrupts from all PHYs.
> */
> static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32 threshold)
> {
> + struct device *dev = ice_pf_to_dev(pf);
> struct ice_hw *hw = &pf->hw;
> - int err = 0;
> - int quad;
> - u32 val;
>
> ice_ptp_reset_ts_memory(hw);
>
> - for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) {
> - err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
> - &val);
> - if (err)
> - break;
> -
> - if (ena) {
> - val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
> - val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
> - val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M,
> - threshold);
> - } else {
> - val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
> + switch (hw->ptp.phy_model) {
> + case ICE_PHY_E82X: {
> + int quad;
> +
> + for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports);
> + quad++) {
> + int err;
> +
> + err = ice_phy_cfg_intr_e82x(hw, quad, ena, threshold);
> + if (err) {
> + dev_err(dev, "Failed to configure PHY interrupt for quad %d, err %d\n",
> + quad, err);
> + return err;
> + }
> }
>
> - err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
> - val);
> - if (err)
> - break;
> + return 0;
> + }
> + case ICE_PHY_E810:
> + return 0;
> + case ICE_PHY_UNSUP:
> + default:
> + dev_warn(dev, "%s: Unexpected PHY model %d\n", __func__,
> + hw->ptp.phy_model);
> + return -EOPNOTSUPP;
> }
> -
> - if (err)
> - dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
> - err);
> - return err;
> }
>
> /**
> @@ -3010,12 +3011,10 @@ static int ice_ptp_init_owner(struct ice_pf *pf)
> /* Release the global hardware lock */
> ice_ptp_unlock(hw);
>
> - if (!ice_is_e810(hw)) {
> - /* Enable quad interrupts */
> - err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
> - if (err)
> - goto err_exit;
> - }
> + /* Configure PHY interrupt settings */
> + err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
> + if (err)
> + goto err_exit;
>
> /* Ensure we have a clock device */
> err = ice_ptp_create_clock(pf);
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> index c892b966c3b8..12f04ad263c5 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> @@ -2715,6 +2715,37 @@ ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
> return 0;
> }
>
> +/**
> + * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
> + * @hw: pointer to the HW struct
> + * @quad: the timestamp quad
> + * @ena: enable or disable interrupt
> + * @threshold: interrupt threshold
> + *
> + * Configure TX timestamp interrupt for the specified quad
> + */
> +
> +int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)
> +{
> + int err;
> + u32 val;
Reverse Christmas trees.
> +
> + err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
> + if (err)
> + return err;
> +
> + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
> + if (ena) {
> + val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
> + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
> + val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold);
> + }
> +
> + err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
> +
> + return err;
> +}
> +
> /**
> * ice_ptp_init_phy_e82x - initialize PHY parameters
> * @ptp: pointer to the PTP HW struct
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
> index 6246de3bacf3..5645b20a9f87 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
> @@ -265,6 +265,7 @@ int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);
> int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
> int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);
> int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
> +int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);
>
> /* E810 family functions */
> int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
> @@ -342,11 +343,8 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
> #define Q_REG_TX_MEM_GBL_CFG 0xC08
> #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
> #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
> -#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
> #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
> -#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
> #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
> -#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
> #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
>
> /* Tx Timestamp data registers */
> --
> 2.43.0
>
>
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