phc-discussions - Re: [PHC] die area estimates (Re: [PHC] GPU multiplication speed?)

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Date: Thu, 27 Feb 2014 21:10:31 -0500
From: Bill Cox <waywardgeek@...il.com>
To: discussions@...sword-hashing.net
Subject: Re: [PHC] die area estimates (Re: [PHC] GPU multiplication speed?)

On Thu, Feb 27, 2014 at 8:45 PM, Bill Cox <waywardgeek@...il.com> wrote:
> With 4-to-1, and just a carry-save multiplier, I'd get 32x32x4 = 4K
> bits... but you ware saying bytes, right?  Are we having a big-B
> little-b communication thing?  I hate those...
>
> Bill

No... naturally it was a communication thing on my side.  I said:

> 8 or 16 32x32->64 multipliers will never take up much area on a 28nm
> ASIC compared to the cache or external memories feeding them  A 4KiB
> cache should be a few times bigger, I think.  You're going to have to...

I meant a few times (as in 8-ish) bigger than a single multiplier, not 8 or 16.

That feels about right with +/- 2X to me.  One 4KiB cache, and maybe
8-ish multipliers... maybe 6... feels closer.

I doubt you could see a 28nm 4KiB cache ram without a magnifying
glass... unless you've got really good vision.  I think there'd be a
lot more than 4K of them on a chip, and even more multipliers than
that.

Just checking my guestimate... a direct shrink of my own 4K-bit SRAM
should be a bit larger than 2000 square microns in 28nm.  That's over
400 of them per mm^2.  I'd guess roughly that 400 32x32->64 bit
multipliers fit per mm^2.

Bill

Bill