[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <200311212252.13985.arny@ats.s.bawue.de>
Date: Fri, 21 Nov 2003 22:52:07 +0100
From: Thilo Schulz <arny@....s.bawue.de>
To: bugtraq@...urityfocus.com
Subject: Re: [aadams@...urityfocus.com: Linux Kernel <= 2.4.21 MXCSR Local DOS Exploitation]
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On Friday 21 November 2003 01:10, David Ahmad wrote:
> Starting with the P3, Intel processors included SSE support which amongst
> many other things added the MXCSR register to handle SSE status and
> control information (and various behavioral flags). MXCSR is a 32-bit
> register, the MSB 16-bits of which are reserved. Intel specifies that if
> these reserved bits are written to a general protection fault (#GP) will
> occur.
An interesting question is: does this problem apply to AMD Processors as well
if /proc/cpuinfo has sse included in the cpuflags?
Anyone able to clear this issue up?
- --
- Thilo Schulz
My public GnuPG key is available at http://home.bawue.de/~arny/public_key.asc
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.3 (GNU/Linux)
iD8DBQE/vokKZx4hBtWQhl4RAr5RAJ91NUJcUxE5+XQDCZC2HgQ9UloauACfU+EI
NkylHPZY/s6RuNViJOmvE5M=
=/ETc
-----END PGP SIGNATURE-----
Powered by blists - more mailing lists