linux-hardening - [RFC PATCH 6/9] arm64: smccc: create proper stack frames for HVC/SMC calls

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Message-Id: <20211013152243.2216899-7-ardb@kernel.org>
Date:   Wed, 13 Oct 2021 17:22:40 +0200
From:   Ard Biesheuvel <ardb@...nel.org>
To:     linux-arm-kernel@...ts.infradead.org
Cc:     linux-hardening@...r.kernel.org, mark.rutland@....com,
        catalin.marinas@....com, will@...nel.org,
        Ard Biesheuvel <ardb@...nel.org>
Subject: [RFC PATCH 6/9] arm64: smccc: create proper stack frames for HVC/SMC calls

Create proper stack frames using the provided macros for HVC/SMC calling
helpers that use the stack. This adds the PAC return address signing
when enabled, and ensures that the unwinder can deal with occurrences
of these routines appearing on the call stack.

Signed-off-by: Ard Biesheuvel <ardb@...nel.org>
---
 arch/arm64/kernel/smccc-call.S | 40 +++++++++-----------
 1 file changed, 17 insertions(+), 23 deletions(-)

diff --git a/arch/arm64/kernel/smccc-call.S b/arch/arm64/kernel/smccc-call.S
index 487381164ff6..b1864880159a 100644
--- a/arch/arm64/kernel/smccc-call.S
+++ b/arch/arm64/kernel/smccc-call.S
@@ -32,8 +32,7 @@ SYM_FUNC_END(__arm_smccc_sve_check)
 EXPORT_SYMBOL(__arm_smccc_sve_check)
 
 	.macro SMCCC instr
-	stp     x29, x30, [sp, #-16]!
-	mov	x29, sp
+	frame_push 0
 alternative_if ARM64_SVE
 	bl	__arm_smccc_sve_check
 alternative_else_nop_endif
@@ -47,7 +46,7 @@ alternative_else_nop_endif
 	cmp	x9, #ARM_SMCCC_QUIRK_QCOM_A6
 	b.ne	1f
 	str	x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
-1:	ldp     x29, x30, [sp], #16
+1:	frame_pop
 	ret
 	.endm
 
@@ -74,11 +73,10 @@ SYM_FUNC_END(__arm_smccc_hvc)
 EXPORT_SYMBOL(__arm_smccc_hvc)
 
 	.macro SMCCC_1_2 instr
-	/* Save `res` and free a GPR that won't be clobbered */
-	stp     x1, x19, [sp, #-16]!
+	frame_push 2
 
-	/* Ensure `args` won't be clobbered while loading regs in next step */
-	mov	x19, x0
+	mov	x19, x0		// preserve args
+	mov	x20, x1		// preserve res
 
 	/* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
 	ldp	x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
@@ -93,24 +91,20 @@ EXPORT_SYMBOL(__arm_smccc_hvc)
 
 	\instr #0
 
-	/* Load the `res` from the stack */
-	ldr	x19, [sp]
-
 	/* Store the registers x0 - x17 into the result structure */
-	stp	x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
-	stp	x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
-	stp	x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
-	stp	x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
-	stp	x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
-	stp	x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
-	stp	x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
-	stp	x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
-	stp	x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
-
-	/* Restore original x19 */
-	ldp     xzr, x19, [sp], #16
+	stp	x0, x1, [x20, #ARM_SMCCC_1_2_REGS_X0_OFFS]
+	stp	x2, x3, [x20, #ARM_SMCCC_1_2_REGS_X2_OFFS]
+	stp	x4, x5, [x20, #ARM_SMCCC_1_2_REGS_X4_OFFS]
+	stp	x6, x7, [x20, #ARM_SMCCC_1_2_REGS_X6_OFFS]
+	stp	x8, x9, [x20, #ARM_SMCCC_1_2_REGS_X8_OFFS]
+	stp	x10, x11, [x20, #ARM_SMCCC_1_2_REGS_X10_OFFS]
+	stp	x12, x13, [x20, #ARM_SMCCC_1_2_REGS_X12_OFFS]
+	stp	x14, x15, [x20, #ARM_SMCCC_1_2_REGS_X14_OFFS]
+	stp	x16, x17, [x20, #ARM_SMCCC_1_2_REGS_X16_OFFS]
+
+	frame_pop
 	ret
-.endm
+	.endm
 
 /*
  * void arm_smccc_1_2_hvc(const struct arm_smccc_1_2_regs *args,
-- 
2.30.2