linux-hardening - Re: [PATCH 8/9] arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Tue, 8 Nov 2022 10:06:45 +0100
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Bjorn Andersson <andersson@...nel.org>
Cc:     agross@...nel.org, konrad.dybcio@...ainline.org,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        lee@...nel.org, ulf.hansson@...aro.org,
        srinivas.kandagatla@...aro.org, jic23@...nel.org, lars@...afoo.de,
        keescook@...omium.org, tony.luck@...el.com, gpiccoli@...lia.com,
        bhupesh.sharma@...aro.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-mmc@...r.kernel.org, linux-iio@...r.kernel.org,
        linux-hardening@...r.kernel.org, marijn.suijten@...ainline.org,
        kernel@...labora.com, luca@...tu.xyz, a39.skl@...il.com,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...ainline.org>
Subject: Re: [PATCH 8/9] arm64: dts: qcom: Add DTS for MSM8976 and MSM8956
 SoCs

Il 08/11/22 05:55, Bjorn Andersson ha scritto:
> On Fri, Nov 04, 2022 at 06:21:21PM +0100, AngeloGioacchino Del Regno wrote:
>> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
>>
>> This commit adds device trees for MSM8956 and MSM8976 SoCs.
>> They are *almost* identical, with minor differences, such as
>> MSM8956 having two A72 cores less.
>>
>> However, there is a bug in Sony Loire bootloader that requires presence
>> of all 8 cores in the cpu{} node, so these will not be deleted.
>>
>> Co-developed-by: Konrad Dybcio <konrad.dybcio@...ainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@...ainline.org>
>> Co-developed-by: Marijn Suijten <marijn.suijten@...ainline.org>
>> Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>

Hello,

Thanks to everyone for the feedback!
I'll send a new version this Friday, according to the received reviews.

In the meanwhile, a few answers will follow, check below.

>> ---
>>   arch/arm64/boot/dts/qcom/msm8956.dtsi |   18 +
>>   arch/arm64/boot/dts/qcom/msm8976.dtsi | 1208 +++++++++++++++++++++++++
>>   2 files changed, 1226 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/msm8956.dtsi
>>   create mode 100644 arch/arm64/boot/dts/qcom/msm8976.dtsi
>>

..snip..

>> +		cpu-map {
>> +			cluster0 {
>> +				core0 {
>> +					cpu = <&CPU0>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&CPU1>;
>> +				};
>> +
>> +				core2 {
>> +					cpu = <&CPU2>;
>> +				};
>> +
>> +				core3 {
>> +					cpu = <&CPU3>;
>> +				};
>> +			};
>> +
>> +			cluster1 {
> 
> Are you sure that the two clusters should be expressed separately in the
> cpu-map?
> 

This SoC has two clusters with split L2 cache, can shutdown one cluster CPU, or
the L2 cache for one cluster, or one entire cluster, hence can also manage idle
states on a per-cluster basis.

Also, as per bindings/cpu/cpu-topology.txt - I am here describing the hierarchy
of CPUs in MSM8976, containing one "little" cluster, composed of four slower CPU
cores and its own L2 cache slice, and one "big" cluster, composed of four (8976)
or two (8956) faster CPU cores and its own L2 cache slice.

That said, I am sure that the two clusters shall be expressed separately.

Am I underestimating and/or ignoring anything?

>> +				core0 {
>> +					cpu = <&CPU4>;
>> +				};
>> +

..snip..

>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		cont_splash_mem: memory@...00000 {
> 
> memory is "reserved", please use specific node names for these regions.
> 

Agreed.

>> +			reg = <0x0 0x83000000 0x0 0x2800000>;
>> +		};
> [..]
>> +		apcs: syscon@...1000 {
>> +			compatible = "syscon";
> 
> Why not use qcom,msm8976-apcs-kpss-global here?
> 

There's no reason not to use the suggested compatible. I'm sorry for the miss.

>> +			reg = <0x0b011000 0x1000>;
>> +		};
> [..]
>> +
>> +		imem: imem@...0000 {
>> +			compatible = "simple-mfd";
> 
> sram/qcom,imem.yaml please.
> 

Will do on v2.

Regards,
Angelo