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Message-ID: <e0a61158-6278-45bc-bc5c-fe35227bdbf1@oss.qualcomm.com>
Date: Wed, 23 Apr 2025 14:18:05 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Danila Tikhonov <danila@...xyga.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Viresh Kumar <viresh.kumar@...aro.org>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck
<linux@...ck-us.net>,
Rajendra Nayak <quic_rjendra@...cinc.com>,
Jassi Brar <jassisinghbrar@...il.com>,
Bjorn Andersson
<andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Amit Kucheria <amitk@...nel.org>,
Thara Gopinath <thara.gopinath@...il.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Zhang Rui <rui.zhang@...el.com>, Lukasz Luba <lukasz.luba@....com>,
Thomas Gleixner <tglx@...utronix.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Wesley Cheng <quic_wcheng@...cinc.com>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Ulf Hansson <ulf.hansson@...aro.org>,
Souradeep Chowdhury <quic_schowdhu@...cinc.com>,
Lee Jones <lee@...nel.org>, Andrew Lunn <andrew+netdev@...n.ch>,
"David S . Miller"
<davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, Alex Elder <elder@...nel.org>,
Alim Akhtar <alim.akhtar@...sung.com>,
Avri Altman <avri.altman@....com>,
Bart Van Assche <bvanassche@....org>, Andy Gross <agross@...nel.org>,
Srinivas Kandagatla <srini@...nel.org>,
Herbert Xu <herbert@...dor.apana.org.au>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Georgi Djakov <djakov@...nel.org>,
Loic Poulain <loic.poulain@....qualcomm.com>,
Robert Foss
<rfoss@...nel.org>, Andi Shyti <andi.shyti@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Taniya Das <quic_tdas@...cinc.com>,
Sibi Sankar <quic_sibis@...cinc.com>, Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>, Joerg Roedel <joro@...tes.org>,
Imran Shaik <quic_imrashai@...cinc.com>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Bartosz Golaszewski <bartosz.golaszewski@...aro.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Jessica Zhang <quic_jesszhan@...cinc.com>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, Kees Cook <kees@...nel.org>,
Tony Luck <tony.luck@...el.com>,
"Guilherme G . Piccoli" <gpiccoli@...lia.com>,
David Wronek <david@...nlining.org>,
Jens Reidel <adrian@...nlining.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-watchdog@...r.kernel.org, linux-usb@...r.kernel.org,
linux-phy@...ts.infradead.org, linux-mmc@...r.kernel.org,
netdev@...r.kernel.org, linux-scsi@...r.kernel.org,
dmaengine@...r.kernel.org, linux-crypto@...r.kernel.org,
linux-i2c@...r.kernel.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev,
linux-remoteproc@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-hardening@...r.kernel.org, linux@...nlining.org,
~postmarketos/upstreaming@...ts.sr.ht
Subject: Re: [PATCH 30/33] arm64: dts: qcom: Add dtsi for Snapdragon
730/730g/732g (SM7150) SoCs
On 4/22/25 11:31 PM, Danila Tikhonov wrote:
> Add base dtsi for SM7150-AA/SM7150-AB/SM7150-AC SoCs
>
> Co-developed-by: David Wronek <david@...nlining.org>
> Signed-off-by: David Wronek <david@...nlining.org>
> Co-developed-by: Jens Reidel <adrian@...nlining.org>
> Signed-off-by: Jens Reidel <adrian@...nlining.org>
> Signed-off-by: Danila Tikhonov <danila@...xyga.com>
> ---
[...]
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo470";
Please split this into Kryo 470 silver and gold, with the former being
based on CA55 and the latter on CA76
[...]
> + pmu-a55 {
> + compatible = "arm,cortex-a55-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + pmu-a76 {
> + compatible = "arm,cortex-a78-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
Please update this, mimicking
2c06e0797c32 ("arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs")
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + cpu_pd0: power-domain-cpu0 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&little_cpu_sleep_0
> + &little_cpu_sleep_1>;
<&foo>,
<&foo2>;
because they are phandles to separate things - DTC treats them equally
though..
[...]
> + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
Paths involving AMPSS_M0 (the cpu endpoint) should be ACTIVE_ONLY,
this applies to the entire file and all paths
[...]
> + remoteproc_adsp: remoteproc@...00000 {
> + compatible = "qcom,sm7150-adsp-pas";
> + reg = <0x0 0x62400000 0x0 0x100>;
This region is 0x10_000 long
[...]
> + adreno_smmu: iommu@...0000 {
> + compatible = "qcom,sm7150-smmu-v2",
> + "qcom,adreno-smmu",
> + "qcom,smmu-v2";
> + reg = <0x0 0x05040000 0x0 0x10000>;
> +
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&gpucc GPU_CC_AHB_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
> + clock-names = "ahb",
> + "bus",
> + "iface";
> +
> + power-domains = <&gpucc CX_GDSC>;
> +
> + #iommu-cells = <1>;
> + #global-interrupts = <2>;
Add `dma-coherent` and check whether the GPU still works
[...]
> + };
> +
> + gmu: gmu@...a000 {
> + compatible = "qcom,adreno-gmu-618.0",
> + "qcom,adreno-gmu";
> + reg = <0x0 0x0506a000 0x0 0x31000>,
Make it 0x26_000 so that it doesn't leak into GPU_CC
[...]
> + tsens0: thermal-sensor@...3000 {
> + compatible = "qcom,sm7150-tsens",
> + "qcom,tsens-v2";
> + reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */
> + <0x0 0x0c222000 0x0 0x1ff>; /* SROT */
Please remove these comments
[...]
> + intc: interrupt-controller@...00000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
> + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
And these ones too
[...]
> + thermal-zones {
Please adjust this against
https://lore.kernel.org/linux-arm-msm/20250219-x1e80100-thermal-fixes-v1-0-d110e44ac3f9@linaro.org/
(keep only critical trips with no sw cooling for the CPU, etc.)
Konrad
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