linux-hardening - Re: [PATCH net-next v5 02/14] docs: networking: Add PPE driver documentation for Qualcomm IPQ9574 SoC

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Message-ID: <1540e0e2-0965-4f75-a1ee-3c7932dc6856@quicinc.com>
Date: Fri, 27 Jun 2025 21:09:23 +0800
From: Lei Wei <quic_leiwei@...cinc.com>
To: Randy Dunlap <rdunlap@...radead.org>, Luo Jie <quic_luoj@...cinc.com>,
        Andrew Lunn <andrew+netdev@...n.ch>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
        "Paolo
 Abeni" <pabeni@...hat.com>, Rob Herring <robh@...nel.org>,
        Krzysztof
 Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Suruchi
 Agarwal <quic_suruchia@...cinc.com>,
        Pavithra R <quic_pavir@...cinc.com>, "Simon Horman" <horms@...nel.org>,
        Jonathan Corbet <corbet@....net>, Kees
 Cook <kees@...nel.org>,
        "Gustavo A. R. Silva" <gustavoars@...nel.org>,
        "Philipp Zabel" <p.zabel@...gutronix.de>
CC: <linux-arm-msm@...r.kernel.org>, <netdev@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-doc@...r.kernel.org>, <linux-hardening@...r.kernel.org>,
        <quic_kkumarcs@...cinc.com>, <quic_linchen@...cinc.com>
Subject: Re: [PATCH net-next v5 02/14] docs: networking: Add PPE driver
 documentation for Qualcomm IPQ9574 SoC



On 6/27/2025 6:02 AM, Randy Dunlap wrote:
> Hi--
> 
> On 6/26/25 7:31 AM, Luo Jie wrote:
>> +Below is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and
>> +other blocks which are in the SoC but outside the PPE engine. These blocks work together
>> +to enable the Ethernet for the IPQ SoC::
>> +
> 
> [snip]
> 
>> + | |              +-------------------------+ +---------+ +---------+         | |
>> + | |125/312.5M clk|       (PCS0)            | | (PCS1)  | | (PCS2)  | pcs ops | |
>> + | +--------------+       UNIPHY0           | | UNIPHY1 | | UNIPHY2 |<--------+ |
>> + +--------------->|                         | |         | |         |           |
>> + | 31.25M ref clk +-------------------------+ +---------+ +---------+           |
>> + |                   |     |      |      |          |          |                |
>> + |              +-----------------------------------------------------+         |
>> + |25/50M ref clk| +-------------------------+    +------+   +------+  | link    |
>> + +------------->| |      QUAD PHY           |    | PHY4 |   | PHY5 |  |---------+
>> +                | +-------------------------+    +------+   +------+  | change
>> +                |                                                     |
>> +                |                       MDIO bus                      |
>> +                +-----------------------------------------------------+
> 
> Does the 'M' on the clk signals on the left side mean megahertz (MHz)?
> I guess that it does, but it was a little confusing when I first saw it.
>

Yes, it means megahertz (MHz). I will update 'M' to 'MHz' in next update.

> Thanks.