linux-hardening - Re: [PATCH v5 4/4] i3c: master: Add basic driver for the Renesas I3C controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAMuHMdX5BfNm1GJ8UyqftcVc07p1aodXuVHxNaYWDYLHaxzXMw@mail.gmail.com>
Date: Wed, 30 Jul 2025 16:39:46 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Wolfram Sang <wsa+renesas@...g-engineering.com>
Cc: linux-renesas-soc@...r.kernel.org, 
	Tommaso Merciai <tommaso.merciai.xr@...renesas.com>, Frank Li <Frank.Li@....com>, 
	Alexandre Belloni <alexandre.belloni@...tlin.com>, Kees Cook <kees@...nel.org>, 
	"Gustavo A. R. Silva" <gustavoars@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>, 
	Magnus Damm <magnus.damm@...il.com>, linux-i3c@...ts.infradead.org, 
	linux-hardening@...r.kernel.org
Subject: Re: [PATCH v5 4/4] i3c: master: Add basic driver for the Renesas I3C controller

Hi Wolfram,

On Thu, 24 Jul 2025 at 11:41, Wolfram Sang
<wsa+renesas@...g-engineering.com> wrote:
> Add a basic driver for the I3C controller found in Renesas RZ/G3S and
> G3E SoCs. Support I3C pure busses (tested with two targets) and mixed
> busses (two I3C devices plus various I2C targets). DAA and communication
> with temperature sensors worked reliably at various speeds.
>
> Missing features such as IBI, HotJoin, and target mode will be added
> incrementally.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
> Tested-by: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
> Reviewed-by: Frank Li <Frank.Li@....com>

Thanks for your patch!

Just a few stylistic comments for now...

> --- /dev/null
> +++ b/drivers/i3c/master/renesas-i3c.c

> +#define REFCKCTL               0x70
> +#define  REFCKCTL_IREFCKS(x)   FIELD_PREP(GENMASK(2, 0), x)

Interesting... Usually the FIELD_*() macros are used like this:

    #define REFCKCTL_IREFCKS    GENMASK(2, 0)

    x = readl(base + REFCKCTL);
    a = FIELD_GET(REFCKCTL_IREFCKS, x);

    y = FIELD_PREP(REFCKCTL_IREFCKS, b);
    writel(y, base + REFCKCTL);

That way you do not have to duplicate "GENMASK(2, 0)" in the read and
write marshalling macros.  But I do agree this driver does not seem
to have register fields that are both read and written ;-)

> +static inline u32 renesas_readl(void __iomem *base, u32 reg)
> +{
> +       return readl(base + reg);
> +}
> +
> +static inline void renesas_writel(void __iomem *base, u32 reg, u32 val)
> +{
> +       writel(val, base + reg);
> +}

Why not use readl() and writel() directly?
To make it easier to add debug prints during initial development?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds