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Date: Tue, 18 Nov 2025 07:59:20 +0000
From: Ankit Agrawal <ankita@...dia.com>
To: Leon Romanovsky <leon@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
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Tian <kevin.tian@...el.com>, Alex Williamson <alex@...zbot.org>
CC: Krishnakant Jaju <kjaju@...dia.com>, Matt Ochs <mochs@...dia.com>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
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<kvm@...r.kernel.org>, "linux-hardening@...r.kernel.org"
<linux-hardening@...r.kernel.org>, Alex Mastro <amastro@...com>, Nicolin Chen
<nicolinc@...dia.com>
Subject: Re: [PATCH v8 11/11] vfio/nvgrace: Support get_dmabuf_phys
+ if (nvdev->resmem.memlength && region_index == RESMEM_REGION_INDEX) {
+ /*
+ * The P2P properties of the non-BAR memory is the same as the
+ * BAR memory, so just use the provider for index 0. Someday
+ * when CXL gets P2P support we could create CXLish providers
+ * for the non-BAR memory.
+ */
+ mem_region = &nvdev->resmem;
+ } else if (region_index == USEMEM_REGION_INDEX) {
+ /*
+ * This is actually cachable memory and isn't treated as P2P in
+ * the chip. For now we have no way to push cachable memory
+ * through everything and the Grace HW doesn't care what caching
+ * attribute is programmed into the SMMU. So use BAR 0.
+ */
+ mem_region = &nvdev->usemem;
+ }
+
Can we replace this with nvgrace_gpu_memregion()?
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