| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <200608231322.44106.ak@suse.de> Date: Wed, 23 Aug 2006 13:22:44 +0200 From: Andi Kleen <ak@...e.de> To: eranian@....hp.com Cc: linux-kernel@...r.kernel.org Subject: Re: [PATCH 18/18] 2.6.17.9 perfmon2 patch for review: new x86_64 files > I have a second thought on this. AMD has architected the performance counters. Quote: >> Implementations are not required to support the performance c o u n t e rs and the event-select registers, or the time-stamp counter. The presence of these features can be determined by << Also all code I've seen checked the family at least. > Their specification is not part of a model specific documentation but > part of the AMD64 architecure. The high level specification is, but not the actual counters for once. > What I don't not quite understand with the K7, K8 terminology is the > relation/dependencies with the AMD64 architecture specification. AMD64 gives a high level register format, K7/K8 is the actual list of performance counters. -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists