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Date:	Thu, 24 Aug 2006 23:24:18 +0100
From:	Matthew Garrett <mjg59@...f.ucam.org>
To:	Arjan van de Ven <arjan@...ux.intel.com>
Cc:	linux-kernel@...r.kernel.org, len.brown@...el.com
Subject: Re: [RFC] maximum latency tracking infrastructure

On Thu, Aug 24, 2006 at 07:41:35PM +0200, Arjan van de Ven wrote:

> +	/* the ipw2100 hardware really doesn't want power management delays
> +	 * longer than 500usec
> +	 */
> +	modify_acceptable_latency("ipw2100", 500);
> +

Hm. My BIOS claims that the C3 transition period is 85usec (and even my 
C4 is 185) , but I've hit the error path where C3 gets disabled. Is this 
really adequate? Also, by the looks of it, the C3 disabling path is 
still present - is it still theoretically necessary with the above, or 
is this just a belt and braces approach?

-- 
Matthew Garrett | mjg59@...f.ucam.org
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