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Message-Id: <1157632405.14882.27.camel@laptopd505.fenrus.org>
Date: Thu, 07 Sep 2006 14:33:25 +0200
From: Arjan van de Ven <arjan@...radead.org>
To: Matthew Wilcox <matthew@....cx>
Cc: Tejun Heo <htejun@...il.com>, linux-pci@...ey.karlin.mff.cuni.cz,
Greg KH <greg@...ah.com>, lkml <linux-kernel@...r.kernel.org>
Subject: Re: question regarding cacheline size
>
> So I think we should redo the PCI subsystem to set cacheline size during
> the buswalk rather than waiting for drivers to ask for it to be set.
... while allowing for quirks for devices that go puke when this
register gets written ;)
(afaik there are a few)
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