linux-kernel - Re: question regarding cacheline size

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <45001EE3.1070500@garzik.org>
Date:	Thu, 07 Sep 2006 09:30:11 -0400
From:	Jeff Garzik <jeff@...zik.org>
To:	Matthew Wilcox <matthew@....cx>
CC:	Tejun Heo <htejun@...il.com>,
	Arjan van de Ven <arjan@...radead.org>,
	linux-pci@...ey.karlin.mff.cuni.cz, Greg KH <greg@...ah.com>,
	lkml <linux-kernel@...r.kernel.org>
Subject: Re: question regarding cacheline size

Matthew Wilcox wrote:
> On Thu, Sep 07, 2006 at 02:53:57PM +0200, Tejun Heo wrote:
>> The spec says that devices can put additional restriction on supported 
>> cacheline size (IIRC, the example was something like power of two >= or 
>> <= certain size) and should ignore (treat as zero) if unsupported value 
>> is written.  So, there might be need for more low level driver 
>> involvement which knows device restrictions, but I don't know whether 
>> such devices exist.
> 
> That's nothing we can do anything about.  The system cacheline size is
> what it is.  If the device doesn't support it, we can't fall back to a
> different size, it'll cause data corruption.  So we'll just continue on,
> and devices which live up to the spec will act as if we hadn't
> programmed a cache size.  For devices that don't, we'll have the quirk.
> 
> Arguably devices which don't support the real system cacheline size
> would only get data corruption if they used MWI, so we only have to
> prevent them from using MWI; they could use a different cacheline size
> for MRM and MRL without causing data corruption.  But I don't think we
> want to go down that route; do you?

FWIW, there are definitely both ethernet and SATA PCI devices which only 
allow a limited set of values in the cacheline size register... and that 
limited set does not include some of the modern machines.

	Jeff



-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/