linux-kernel - Re: question regarding cacheline size

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Message-ID: <20060907170030.GR2558@parisc-linux.org>
Date:	Thu, 7 Sep 2006 11:00:30 -0600
From:	Matthew Wilcox <matthew@....cx>
To:	Jeff Garzik <jgarzik@...ox.com>
Cc:	Tejun Heo <htejun@...il.com>,
	Grant Grundler <grundler@...isc-linux.org>,
	Arjan van de Ven <arjan@...radead.org>,
	linux-pci@...ey.karlin.mff.cuni.cz, Greg KH <greg@...ah.com>,
	lkml <linux-kernel@...r.kernel.org>
Subject: Re: question regarding cacheline size

On Thu, Sep 07, 2006 at 12:00:39PM -0400, Jeff Garzik wrote:
> Tejun Heo wrote:
> >arch/i386/pci/common.c overrides cacheline size to min 32 regardless of 
> >actual size.  So, we seem to be using larger cacheline size for MWI 
> >already.
> 
> It clamps the minimum size to 32, yes, but on modern machines common.c 
> configures it to a larger size.
> 
> 
> >Jeff pointed out that there actually are devices which limit CLS config. 
> > IMHO, making PCI configure CLS automatically and provide helpers to LLD 
> >to override it if necessary should cut it.
> 
> We still have to add a raft of quirks, if we start automatically 
> configurating CLS...  Also, many PCI devices hardcode it to zero.

That's not a problem.  As long as they silently discard the writes to
the CLS register, we'll cope.  If they decide to flip out, then we have
the no_cls flag.

> If we start configuring CLS automatically, I forsee a period of breakage...

Probably.  But it's something we should have done a long time ago.
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