linux-kernel - Re: Opinion on ordering of writel vs. stores to RAM

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Message-ID: <4503091C.1050501@intel.com>
Date:	Sat, 09 Sep 2006 11:34:04 -0700
From:	Auke Kok <auke-jan.h.kok@...el.com>
To:	Linus Torvalds <torvalds@...l.org>
CC:	Paul Mackerras <paulus@...ba.org>, linux-kernel@...r.kernel.org,
	benh@...nel.crashing.org, akpm@...l.org,
	segher@...nel.crashing.org, davem@...emloft.net
Subject: Re: Opinion on ordering of writel vs. stores to RAM

Linus Torvalds wrote:
> 
> On Sat, 9 Sep 2006, Paul Mackerras wrote:
>> Do you have an opinion about whether the MMIO write in writel() should
>> be ordered with respect to preceding writes to normal memory?
> 
> It shouldn't. It's too expensive. The fact that PC's have nice memory 
> consistency models means that most of the testing is going to be with the 
> PC memory ordering, but the same way we have "smp_wmb()" (which is also a 
> no-op on x86) we should probably have a "mmiowb()" there.
> 
> Gaah. Right now, mmiowb() is actually broken on x86 (it's an empty define, 
> so it may cause compiler warnings about statements with no effects or 
> something).
> 
> I don't think anyting but a few SCSI drivers that are used on some ia64 
> boxes use mmiowb(). And it's currently a no-op not only on x86 but also on 
> powerpc. Probably because it's defined to be a barrier between _two_ MMIO 
> operations, while we should probably have things like

it seems to be a growing virus with network drivers too. bnx2, s2io, tg3 and 
bcm43xx (which has like 40 of them) are already resorting to it. We're even 
planning on putting one in to e1000.

I'm not sure what bcm43xx chip will work with IA64, or if people actually have 
itanium laptops(!) or MIPS, but for e1000 it definately fixes ordering problems 
on IA64.

Auke

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