linux-kernel - Re: Opinion on ordering of writel vs. stores to RAM

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Message-Id: <200609101018.06930.jbarnes@virtuousgeek.org>
Date:	Sun, 10 Sep 2006 10:18:06 -0700
From:	Jesse Barnes <jbarnes@...tuousgeek.org>
To:	David Miller <davem@...emloft.net>
Cc:	jeff@...zik.org, paulus@...ba.org, torvalds@...l.org,
	linux-kernel@...r.kernel.org, benh@...nel.crashing.org,
	akpm@...l.org, segher@...nel.crashing.org
Subject: Re: Opinion on ordering of writel vs. stores to RAM

On Saturday, September 09, 2006 3:08 am, David Miller wrote:
> From: Jeff Garzik <jeff@...zik.org>
> Date: Sat, 09 Sep 2006 05:55:19 -0400
>
> > As (I think) BenH mentioned in another email, the normal way Linux
> > handles these interfaces is for the primary API (readX, writeX) to
> > be strongly ordered, strongly coherent, etc.  And then there is a
> > relaxed version without barriers and syncs, for the smart guys who
> > know what they're doing
>
> Indeed, I think that is the way to handle this.

Well why didn't you guys mention this when mmiowb() went in?

I agree that having a relaxed PIO ordering version of writeX makes sense 
(jejb convinced me of this on irc the other day).  But what to name it?  
We already have readX_relaxed, but that's for PIO vs. DMA ordering, not 
PIO vs. PIO.  To distinguish from that case maybe writeX_weak or 
writeX_nobarrier would make sense?

Jesse
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