linux-kernel - Re: Opinion on ordering of writel vs. stores to RAM

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Message-Id: <1157937023.31071.289.camel@localhost.localdomain>
Date:	Mon, 11 Sep 2006 11:10:23 +1000
From:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
To:	Segher Boessenkool <segher@...nel.crashing.org>
Cc:	Jesse Barnes <jbarnes@...tuousgeek.org>,
	Alan Cox <alan@...rguk.ukuu.org.uk>,
	David Miller <davem@...emloft.net>, jeff@...zik.org,
	paulus@...ba.org, torvalds@...l.org, linux-kernel@...r.kernel.org,
	akpm@...l.org
Subject: Re: Opinion on ordering of writel vs. stores to RAM


> Hence my proposal of calling it pci_cpu_to_cpu_barrier() -- what it
> orders is accesses from separate CPUs.  Oh, and it's bus-specific,
> of course.

I disagree on that one, as I disagree on Jesse terminology too :)

Ordering between stores issued by different CPUs has no meaning
whatsoever unless you have locks. That is you have some kind of
synchronisation primitive between the 2 CPUs. Outside of that, the
concept of ordering doesn't make any sense.

Thus the problem is really only of MMIO stores leaking out of locks,
thus it's really a MMIO vs. lock barrier, and it's a lot easier to
understand that way imho.

Ben.


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