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Message-Id: <52D5A4D1-ACE2-4D55-A01D-135FEC606B85@kernel.crashing.org>
Date:	Mon, 11 Sep 2006 19:21:22 +0200
From:	Segher Boessenkool <segher@...nel.crashing.org>
To:	paulmck@...ibm.com
Cc:	Alan Stern <stern@...land.harvard.edu>,
	Oliver Neukum <oliver@...kum.org>,
	David Howells <dhowells@...hat.com>,
	Kernel development list <linux-kernel@...r.kernel.org>
Subject: Re: Uses for memory barriers

> 2.	All stores to a given single memory location will be perceived
> 	as having occurred in the same order by all CPUs.

All CPUs that _do_ see two stores to the same memory location happening,
will see them occurring in the same order -- not all CPUs seeing a
later store will necessarily see the earlier stores.


Segher

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