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Date: Mon, 11 Sep 2006 11:12:29 -0700 From: Jesse Barnes <jbarnes@...tuousgeek.org> To: Segher Boessenkool <segher@...nel.crashing.org> Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>, Alan Cox <alan@...rguk.ukuu.org.uk>, David Miller <davem@...emloft.net>, jeff@...zik.org, paulus@...ba.org, torvalds@...l.org, linux-kernel@...r.kernel.org, akpm@...l.org Subject: Re: Opinion on ordering of writel vs. stores to RAM On Sunday, September 10, 2006 5:54 pm, Segher Boessenkool wrote: > >> - writel/readl become totally ordered (including vs. memory). > >> Basically x86-like. Expensive (very expensive even on some > >> architectures) but also very safe. > > > > This approach will minimize driver changes, and would imply the > > removal > > of some existing mmiowb() and wmb() macros. > > Like I tried to explain already, in my competing approach, no drivers > would need changes either. And you could remove those macro's (or > their more-verbosely-saying-what-their-doing, preferably bus-specific > as well) as well -- but you'll face the wrath of those who care about > performance of those drivers on non-x86 platforms. Right, at the cost of more complexity in the accessor routines. > Hence my proposal of calling it pci_cpu_to_cpu_barrier() -- what it > orders is accesses from separate CPUs. Oh, and it's bus-specific, > of course. Makes sense to me, I have no problem with that name since it's really intended to order posted PCI writes from different CPUs. Jesse - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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