linux-kernel - Re: [RFC] MMIO accessors & barriers documentation

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Date:	Mon, 11 Sep 2006 19:24:32 -0400
From:	Jeff Garzik <jgarzik@...ox.com>
To:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
CC:	Jesse Barnes <jbarnes@...tuousgeek.org>,
	Linux Kernel list <linux-kernel@...r.kernel.org>,
	Alan Cox <alan@...rguk.ukuu.org.uk>,
	"David S. Miller" <davem@...emloft.net>,
	Paul Mackerras <paulus@...ba.org>,
	Linus Torvalds <torvalds@...l.org>,
	Andrew Morton <akpm@...l.org>,
	Segher Boessenkool <segher@...nel.crashing.org>
Subject: Re: [RFC] MMIO accessors & barriers documentation

Benjamin Herrenschmidt wrote:
> Well, the argument currently is to make writel and readl imply the above
> barriers by making them fully ordered (and slow on some platforms) and
> so also provide more weakly ordered routines along with barriers for
> people who know what they do. The above 2 barriers are what I've called
> io_to_memory_rb() and memory_to_io_wb() (actually,
> prepare_to_read_dma_memory() by itself doesn't really make much sense.
> It does in conjunction with an MMIO read to flush DMA buffers, in which
> case the barrier provides an ordering guarantee that the memory reads
> will only be performed after the MMIO read has fully completed).

<jgarzik throws a monkey wrench into the works>

I think focusing on MMIO just confuses the issue.

wmb() is often used to make sure a memory store is visible to a 
busmastering PCI device... before the code proceeds with some more 
transactions in the memory space shared by the host and PCI device.

prepare_to_read_dma_memory() is the operation that an ethernet driver's 
RX code wants.  And this is _completely_ unrelated to MMIO.  It just 
wants to make sure that the device and host are looking at the same 
data.  Often this involves polling a DMA descriptor (or index, stored 
inside DMA-able memory) looking for changes.

flush_my_writes_to_dma_memory() is the operation that an ethernet 
driver's TX code wants, to precede either an MMIO "poke" or any other 
non-MMIO operation where the driver needs to be certain that the write 
is visible to the PCI device, should the PCI device desire to read that 
area of memory.

	Jeff

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