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Message-ID: <787b0d920609112233u16a1cbcv2bf4ffa6b378dcd7@mail.gmail.com>
Date: Tue, 12 Sep 2006 01:33:21 -0400
From: "Albert Cahalan" <acahalan@...il.com>
To: benh@...nel.crashing.org, linux-kernel@...r.kernel.org,
jbarnes@...tuousgeek.org, alan@...rguk.ukuu.org.uk,
davem@...emloft.net, jgarzik@...ox.com, paulus@...ba.org,
torvalds@...l.org, akpm@...l.org, segher@...nel.crashing.org
Subject: Re: [RFC] MMIO accessors & barriers documentation
Benjamin Herrenschmidt writes:
> 1- io_to_io_barrier() : This barrier provides ordering requirement #1
> between two MMIO accesses. It's to be used in conjuction with fully
> relaxed accessors of Class 3.
>
> 2- memory_to_io_wb() : This barrier provides ordering requirement #2
> between a memory store and an MMIO store. It can be used in conjunction
> with write accessors of Class 2 and 3.
>
> 3- io_to_memory_rb(value) : This barrier provides ordering requirement
> #3 between an MMIO read and a subsequent read from memory. For
> implementation purposes on some architectures, the value actually read
> by the MMIO read shall be passed as an argument to this barrier. (This
> allows to generate the appropriate CPU instruction magic to force the
> CPU to consider the value as being "used" and thus force the read to be
> performed immediately). It can be used in conjunction with read
> accessors of Class 2 and 3
>
> 4- io_to_lock_wb() : This barrier provides ordering requirement #4
> between an MMIO store and a subsequent spin_unlock(). It can be used in
> conjunction with write accessors of Class 2 and 3.
These can really multiply: read or write, RAM and various types
of IO space, etc.
Let's have a generic arch-provided macro and let gcc do some work
for us.
Example usage:
fence(FENCE_READ_RAM|FENCE_READ_PCI_IO, FENCE_WRITE_PCI_MMIO);
Example implementation for PowerPC:
#define PPC_RAM (FENCE_READ_RAM|FENCE_WRITE_RAM)
#define PPC_MMIO (FENCE_READ_PCI_MMIO|FENCE_READ_PCI_CONFIG|\
FENCE_READ_PCI_RAM|FENCE_READ_PCI_IO | FENCE_WRITE_PCI_MMIO|\
FENCE_WRITE_PCI_CONFIG|FENCE_WRITE_PCI_RAM|FENCE_WRITE_PCI_IO)
#define PPC_OTHER (~(PPC_RAM|PPC_MMIO))
#define fence(before,after) do{ \
if(before&PPC_RAM && after&PPC_MMIO) \
__asm__ __volatile__ ("sync" : : : "memory"); \
else if(before&PPC_MMIO && after&PPC_RAM) \
__asm__ __volatile__ ("sync" : : : "memory"); \
else if((before|after) & PPC_OTHER) \
__asm__ __volatile__ ("sync" : : : "memory"); \
else if(before && after) \
__asm__ __volatile__ ("eieio" : : : "memory"); \
}while(0)
-
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