linux-kernel - Re: Uses for memory barriers

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Message-ID: <45102E21.2060301@yahoo.com.au>
Date:	Wed, 20 Sep 2006 03:51:29 +1000
From:	Nick Piggin <nickpiggin@...oo.com.au>
To:	Alan Stern <stern@...land.harvard.edu>
CC:	"Paul E. McKenney" <paulmck@...ibm.com>,
	David Howells <dhowells@...hat.com>,
	Kernel development list <linux-kernel@...r.kernel.org>
Subject: Re: Uses for memory barriers

Alan Stern wrote:
> On Wed, 20 Sep 2006, Nick Piggin wrote:

>>I don't think that need be the case if one of the CPUs that has written
>>the variable forwards the store to a subsequent load before it reaches
>>the cache coherency (I could be wrong here). So if that is the case, then
>>your above example would be correct.
> 
> 
> I don't understand your comment.  Are you saying it's possible for two 
> CPUs to observe the same two writes and see them occurring in opposite 
> orders?

If store forwarding is able to occur outside cache coherency protocol,
then I don't see why not. I would also be interested to know if this
is the case on real systems.

-- 
SUSE Labs, Novell Inc.
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