linux-kernel - Re: [PATCH] Linux Kernel Markers

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Date:	Thu, 21 Sep 2006 00:00:41 +0100
From:	Richard J Moore <richardj_moore@...ibm.com>
To:	Alan Cox <alan@...rguk.ukuu.org.uk>
Cc:	Andrew Morton <akpm@...l.org>,
	Mathieu Desnoyers <compudj@...stal.dyndns.org>,
	"Frank Ch. Eigler" <fche@...hat.com>,
	Greg Kroah-Hartman <gregkh@...e.de>,
	Christoph Hellwig <hch@...radead.org>,
	Jes Sorensen <jes@....com>, karim@...rsys.com,
	Paul Mundt <lethal@...ux-sh.org>,
	linux-kernel <linux-kernel@...r.kernel.org>, ltt-dev@...fik.org,
	Martin Bligh <mbligh@...gle.com>,
	Michel Dagenais <michel.dagenais@...ymtl.ca>,
	Ingo Molnar <mingo@...e.hu>, prasanna@...ibm.com,
	systemtap@...rces.redhat.com, Thomas Gleixner <tglx@...utronix.de>,
	William Cohen <wcohen@...hat.com>,
	Tom Zanussi <zanussi@...ibm.com>
Subject: Re: [PATCH] Linux Kernel Markers



Alan Cox <alan@...rguk.ukuu.org.uk> wrote on 20/09/2006 11:44:29:

> Ar Maw, 2006-09-19 am 20:52 -0400, ysgrifennodd Karim Yaghmour:
> > a) the errata & a possible thread having an IP leading back within (not
> >    at the start of) the range to be replaced.
> > b) the errata & replacing single instruction with single instruction of
> >    same size.
>
> Intel don't distinguish. Richard's reply later in the thread answers a
> lot more including what Intels architecture team said about int3 being a
> specific safe case for soem reason
>
> > I was vaguely aware of the issue on x86. Do you know if this applies
the
> > same on other achitectures?
>
> I wouldn't know.

It can for another reason - score-boarding: that's where a byte being
stored assumes intermediate values due to the bits not being set
simultaneously. Generally this doesn't cause a problem because data across
processors is serialised for update by mutexes. However, when applied to
code all sorts of interesting instructions can execute before the bits
settle down. I haven't heard of this troubling Intel, but it does occur on
some current architectures.

Richard

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