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Message-id: <4526F1A8.3020907@shaw.ca>
Date:	Fri, 06 Oct 2006 18:15:36 -0600
From:	Robert Hancock <hancockr@...w.ca>
To:	Jeff Garzik <jeff@...zik.org>,
	linux-kernel <linux-kernel@...r.kernel.org>
Cc:	Matthew Wilcox <matthew@....cx>
Subject: Re: [PATCH 2/2] [TULIP] Check the return value from pci_set_mwi()

Jeff Garzik wrote:
> The unmodified tulip driver checks both MWI and cacheline-size because 
> one of the clones (PNIC or PNIC2) will let you set the MWI bit, but 
> hardwires cacheline size to zero.
> 
> If the arches do not behave consistently, we need to keep the check in 
> the tulip driver, to avoid incorrectly programming the csr0 MWI bit.
> 
>     Jeff

I should think that pci_set_mwi should fail if either the cache line 
size showed 0 (after either setting the correct size or assuming it 
should have been set already) or the MWI bit ended up clear after we 
tried to turn it on.

That pcibios_prep_mwi code for sparc64 looks wrong, if you plug in a 
device that doesn't implement MWI at all it will probably not let 
anything get written to PCI_CACHE_LINE_SIZE other than 0, but it is 
blindly succeeding in all cases. Even if the arch assumes the firmware 
already set the size properly it should still make sure it is non-zero 
before allowing MWI..

-- 
Robert Hancock      Saskatoon, SK, Canada
To email, remove "nospam" from hancockr@...pamshaw.ca
Home Page: http://www.roberthancock.com/

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