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Date:	Tue, 14 Nov 2006 21:30:17 +0100
From:	Andreas Mohr <andi@...x01.fht-esslingen.de>
To:	"Pallipadi, Venkatesh" <venkatesh.pallipadi@...el.com>
Cc:	Andreas Mohr <andi@...x01.fht-esslingen.de>,
	Len Brown <lenb@...nel.org>, Ingo Molnar <mingo@...e.hu>,
	Thomas Gleixner <tglx@...utronix.de>,
	linux-kernel@...r.kernel.org,
	"Van De Ven, Arjan" <arjan.van.de.ven@...el.com>
Subject: Re: CONFIG_NO_HZ: missed ticks, stall (keyb IRQ required) [2.6.18-rc4-mm1]

Hi,

On Tue, Nov 14, 2006 at 10:06:37AM -0800, Pallipadi, Venkatesh wrote:
> >Hmm, hopefully it's easy to research where to enable HPET
> >(if there is one at all!) on an el-cheapo VIA chipset...
> >
> >Many thanks for your patch! (even though currently Intel-only)
> 
> Yes. This should be easy to do for any chipset. It should be documented
> somewhere in the chipset documentation. Atleast it is documented on ICH
> specification :).

OK, I just managed to get hold of both VT8237 *and* VT8235 specs.

VT8237 is documented to have HPET.
The convenient thing is that on VT8235 *exactly* that register space where
8237 has its HPET is marked as "reserved" ;)
(i.e. there's a register hole which has exactly the size of the
HPET range).
IOW, we might be lucky and 8235 already has an initial implementation of
HPET available (which even works??).

OK, so let's provide some more details:
VT8237 has a PCI device 17 function 0 part ("Bus Control and Power Management")
which has a Programmable Chip Select Control block at 0x5D to 0x6B.
Offset 0x68 is HPET Control, RW, which has an Enable bit (default Disabled)
at bit 7 (MSB).
0x69 to 0x6B is HPET Base Address, RW (lower 22 bits, 22-23 "Reserved").
VT8235 has exactly 0x68 to 0x6B "reserved", with valid registers both
before and thereafter.

There's also some register description about APIC timer,
maybe I'll gather something about my C2 headaches from there.

Andreas Mohr
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