linux-kernel - Re: [PATCH] 2.6.18-rt7: PowerPC: fix breakage in threaded fasteoi type IRQ handlers

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4560C409.9030709@ru.mvista.com>
Date:	Sun, 19 Nov 2006 23:52:25 +0300
From:	Sergei Shtylyov <sshtylyov@...mvista.com>
To:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
Cc:	Ingo Molnar <mingo@...e.hu>, linuxppc-dev@...abs.org,
	linux-kernel@...r.kernel.org, dwalker@...sta.com
Subject: Re: [PATCH] 2.6.18-rt7: PowerPC: fix breakage in threaded fasteoi
 type IRQ handlers

Hello.

Benjamin Herrenschmidt wrote:

>>>EOI is a more "high level" thing that some "intelligent" PICs that
>>>automatically raise the priority do to restore the priority to what it
>>>was before the interrupt occured.

>>    Thank you, I know. Even 8259 has the notion of priority and EOI works the 
>>same way here.

> Ok, so why would you need an ack there then while eoi is just what you
> need ? :-)

    Don't ask me, ask the genirq authors. :-)

> Also, that's interesting what you are saying about 8259... I should be
> able to convert ppc's i8259 to use fasteoi too...

    I'm not sure it's feasible. The idea behind level/edge flows is to 
eliminate the interrupt priority I think. That's why they EOI ASAP (with the 
level handler masking IRQ before that) -- this way the other interrupts may 
come thru.
    I used to think that fasteoi was intended for SMP PICs which are 
intelligent enough to mask off the interrupts pending delivery or handling on 
CPUs and unmask them upon receiving EOI -- just like x86 IOAPIC does. This 
way, the acceptance of the lower priority interrupts shouldn't be hindered on 
the other CPUs. Maybe the scheme is different for OpenPIC (I know it has the 
different interrupt distribution scheme from IOAPIC)?

> Ben.

WBR, Sergei
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/