linux-kernel - Re: [PATCH] 2.6.18-rt7: PowerPC: fix breakage in threaded fasteoi type IRQ handlers

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Message-ID: <4561CDB8.2030309@ru.mvista.com>
Date:	Mon, 20 Nov 2006 18:46:00 +0300
From:	Sergei Shtylyov <sshtylyov@...mvista.com>
To:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
Cc:	Ingo Molnar <mingo@...e.hu>, linuxppc-dev@...abs.org,
	linux-kernel@...r.kernel.org, dwalker@...sta.com
Subject: Re: [PATCH] 2.6.18-rt7: PowerPC: fix breakage in threaded fasteoi
 type IRQ handlers

Hello.

Benjamin Herrenschmidt wrote:
>>    I'm not sure it's feasible. The idea behind level/edge flows is to 
>>eliminate the interrupt priority I think. That's why they EOI ASAP (with the 
>>level handler masking IRQ before that) -- this way the other interrupts may 
>>come thru.

> Well, the idea behind the level/edge flow is not exactly that afaik.
> It's more like having tailored handlers for level/edge on PICs that are
> not intelligent to auto-mask with a priority mecanism (ie. dumb PICs
> which are very common in the embedded field, and for example, on ARM
> where genirq takes its roots).

    That was a conclusion to which I came after looking at the 8259 code (that 
PIC being full capable of the priority masking).

>>    I used to think that fasteoi was intended for SMP PICs which are 
>>intelligent enough to mask off the interrupts pending delivery or handling on 
>>CPUs and unmask them upon receiving EOI -- just like x86 IOAPIC does.

> In general, PICs that are intelligent enough to mask off, wether using
> something as you describe or using priorities. I don't feel the need of
> going through hoops to allow lower or same priority interrupts in.
> First, if you really need an interrupt to be serviced quick, then you
> can just give it a higher priority. In the general case however, I do
> -not- want to allow interrupts to stack up. Imagine a big IBM machine
> with hundreds interrupt lines, what happens to the kernel stack if we
> let them interrupt each other ?

    Well, such machines are SMP usually... :-)

>> This 
>>way, the acceptance of the lower priority interrupts shouldn't be hindered on 
>>the other CPUs. Maybe the scheme is different for OpenPIC (I know it has the 
>>different interrupt distribution scheme from IOAPIC)?

> I don't think there is a real need to let lower priority interrupts in
> on a CPU that is currently handling a higher priority one.

    Nevertheless, 8259 drivers are doing exactly this on UP machines -- and 
they were doing this before and after genirq conversion...

> Ben.

WBR, Sergei
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