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Message-ID: <Pine.LNX.4.64.0612061147000.27534@schroedinger.engr.sgi.com>
Date: Wed, 6 Dec 2006 11:47:40 -0800 (PST)
From: Christoph Lameter <clameter@....com>
To: Matthew Wilcox <matthew@....cx>
cc: Linus Torvalds <torvalds@...l.org>,
Russell King <rmk+lkml@....linux.org.uk>,
David Howells <dhowells@...hat.com>,
Andrew Morton <akpm@...l.org>,
linux-arm-kernel@...ts.arm.linux.org.uk,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-arch@...r.kernel.org
Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch
doesn't support it
On Wed, 6 Dec 2006, Matthew Wilcox wrote:
> On Wed, Dec 06, 2006 at 11:29:42AM -0800, Christoph Lameter wrote:
> > On Wed, 6 Dec 2006, Matthew Wilcox wrote:
> >
> > > It's just been pointed out to me that the parisc one isn't safe.
> > >
> > > <dhowells> imagine variable X is set to 3
> > > <dhowells> CPU A issues cmpxchg(&X, 3, 5)
> > > <dhowells> you'd expect that to change X to 5
> > > <dhowells> but what if CPU B assigns 6 to X between cmpxchg reading X
> > > and it setting X?
> >
> > The same could happen with a regular cmpxchg. Cmpxchg changes it to 5 and
> > then other cpu performs a store before the next instruction.
>
> For someone who's advocating use of cmpxchg, it seems you don't
> understand its semantics! In the scenario dhowells pointed out, X would
> be left set to 5. X should have the value 6 under any legitimate
> implementation:
Nope this is a UP implementation. There is no cpu B.
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