linux-kernel - Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch doesn't support it

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Message-ID: <Pine.LNX.4.64.0612081130110.3516@woody.osdl.org>
Date:	Fri, 8 Dec 2006 11:35:39 -0800 (PST)
From:	Linus Torvalds <torvalds@...l.org>
To:	Russell King <rmk+lkml@....linux.org.uk>
cc:	David Howells <dhowells@...hat.com>,
	Christoph Lameter <clameter@....com>,
	Nick Piggin <nickpiggin@...oo.com.au>, akpm@...l.org,
	linux-arm-kernel@...ts.arm.linux.org.uk,
	linux-kernel@...r.kernel.org, linux-arch@...r.kernel.org
Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch
 doesn't support it

On Fri, 8 Dec 2006, Russell King wrote:
>
> Yes you can.  Well, you can on ARM at least.  Between the load exclusive
> you can do anything you like until you hit the store exclusive.  If you
> haven't touched the location (with anything other than another load
> exclusive) and no other CPU has issued a load exclusive, your store
> exclusive succeeds.

Is that actually true?

Almost all LL/SC implementations have granularity rules, where "touch the 
location" is not a byte-granular thing, but actually ends up being 
something like "touch the same cachline".

They also often have _other_ rules like: "the cacheline has to stay in the 
L1 in exclusive state" etc. Which means that in a direct-mapped L1 cache, 
you can't even load anything that might be in the same way, because it 
would cause a cache eviction that invalidates the SC.

It's possible that ARM has really strong LL/SC, but quite frankly, that 
sounds unlikely. I've never heard of anybody ever _architecturally_ saying 
that they support that strong requirements, even if certain micro- 
architectures might actually support stronger semantics than the ones 
guaranteed by the architectural rules.

			Linus
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