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Message-ID: <20070206192533.GB5647@amd.com>
Date: Tue, 6 Feb 2007 20:25:33 +0100
From: "Joerg Roedel" <joerg.roedel@....com>
To: ebiederm@...ssion.com
cc: "Andreas Herrmann" <andreas.herrmann3@....com>, discuss@...-64.org,
"Andi Kleen" <ak@...e.de>, linux-kernel@...r.kernel.org,
"Richard Gooch" <rgooch@...e-mbox.com>
Subject: Re: [discuss] [patch] mtrr: fix issues with large addresses
On Tue, Feb 06, 2007 at 12:08:12PM -0700, ebiederm@...ssion.com wrote:
> "Andreas Herrmann" <andreas.herrmann3@....com> writes:
> > You are referring to current Linux implementation?
> > The AMD64 architecture increased physical address size in PSE mode to
> > 40 bits. So at least it would be possible to use more than 32 bits.
>
> How do you get 40 physical bits in a 32bit page table entry? My memory
> is that the low bits in the page table entry were well defined and
> accounted for. I'm pretty certain I can account for 6 of the low bits
> off the top of my head. PSE is the page size extension allowing pages 2MB/4MB
> pages.
The access to 40 physical address bits is only possible using large pages
(4MB on 32bit without PAE). In those page tables entrys you only use
bits 22:31 for encoding the physical address. The bits 12:21 are
unused. These unused bits are reused to encode bits 32:39 of the 40 bit
physical address.
Joerg
--
Joerg Roedel
Operating System Research Center
AMD Saxony LLC & Co. KG
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