linux-kernel - Re: [PATCH] Add PCI device ID for IT8152 RISC-to-PCI chip

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <45D1CF22.6010706@8d.com>
Date:	Tue, 13 Feb 2007 09:45:54 -0500
From:	Raphael Assenat <raph@...com>
To:	Lennart Sorensen <lsorense@...lub.uwaterloo.ca>
CC:	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] Add PCI device ID for IT8152 RISC-to-PCI chip

Lennart Sorensen wrote:
> On Fri, Feb 09, 2007 at 03:14:05PM -0500, Raphael Assenat wrote:
> 
>>This patch adds a PCI device ID (0x8152) for the IT8152F/G
>>Advanced RISC-to-PCI Companion Chip.
>>
>>-- 
>>Raphael Assenat
>>8D Technologies Inc.
> 
> 
>>This patch adds a PCI device ID for the IT8152F/G 
>>Advanced RISC-to-PCI Companion Chip.
>>
>>Signed-off-by: Raphael Assenat <raph@...com>
>>
>>--- linux-2.6.20/include/linux/pci_ids.h	2007-02-04 13:44:54.000000000 -0500
>>+++ linux-2.6.20-8d/include/linux/pci_ids.h	2007-02-09 15:00:38.000000000 -0500
>>@@ -1626,6 +1626,7 @@
>> #define PCI_VENDOR_ID_ROCKWELL		0x127A
>> 
>> #define PCI_VENDOR_ID_ITE		0x1283
>>+#define PCI_DEVICE_ID_ITE_8152		0x8152
>> #define PCI_DEVICE_ID_ITE_8211		0x8211
>> #define PCI_DEVICE_ID_ITE_8212		0x8212
>> #define PCI_DEVICE_ID_ITE_8872		0x8872
> 
> 
> Oh that one.  Anyone ever have a reliable PCI bus with one of these?
> The one system on a board I have worked with in the past had so many
> problems with the PCI bus that we have to switch to another board
> instead.  Too bad since the ARM cpu was much faster and better and
> handling network traffic (we switched to a Geode SC1200 based board).
> 
> At the time my theory was that the cpu would interrupt DMA transfers
> when it wanted access to system memory, which would break the PCI
> transfers.  But that was just my theory.
Really? I have no idea if it's possible to get a reliable PCI bus or
not with this chip. Right now, we only use it for it's built-in OHCI 
USB host controller and UART. You're making me hope I never have to 
use it for interfacing a PCI card!

Best regards,

-- 
Raphael Assenat
8D Technologies Inc.
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/