linux-kernel - [PATCH] i386 make NMI use PERFCTR1 for architectural perfmon

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Message-ID: <20070217160656.GA16715@frankl.hpl.hp.com>
Date:	Sat, 17 Feb 2007 08:06:56 -0800
From:	Stephane Eranian <eranian@....hp.com>
To:	linux-kernel@...r.kernel.org
Cc:	ak@...e.de, akpm@...ux-foundation.org,
	Stephane Eranian <eranian@....hp.com>
Subject: [PATCH] i386 make NMI use PERFCTR1 for architectural perfmon

Hello,

This patch against 2.6.20 makes the NMI watchdog use PERFSEL1/PERFCTR1
instead of PERFSEL0/PERFCTR0 on processors supporting Intel architectural
perfmon, such as Intel Core 2. Although all PMU events can work on
both counters, the Precise Event-Based Sampling (PEBS) requires that the
event be in PERFCTR0 to work correctly (see section 18.14.4.1 in the
IA32 SDM Vol 3b).

A similar patch for x86-64 is to follow.

Changelog:
	- make the i386 NMI watchdog use PERFSEL1/PERFCTR1 instead of PERFSEL0/PERFCTR0
	  on processors supporting the Intel architectural perfmon (e.g. Core 2 Duo).
	  This allows PEBS to work when the NMI watchdog is active.

signed-off-by: stephane eranian <eranian@....hp.com>


diff -urNp --exclude=.git linux-2.6.20.orig/arch/i386/kernel/nmi.c linux-2.6.20.base/arch/i386/kernel/nmi.c
--- linux-2.6.20.orig/arch/i386/kernel/nmi.c	2007-02-04 10:44:54.000000000 -0800
+++ linux-2.6.20.base/arch/i386/kernel/nmi.c	2007-02-17 07:59:41.000000000 -0800
@@ -288,7 +288,7 @@ static int __init check_nmi_watchdog(voi
 		 * 32nd bit should be 1, for 33.. to be 1.
 		 * Find the appropriate nmi_hz
 		 */
-	 	if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0 &&
+	 	if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1 &&
 			((u64)cpu_khz * 1000) > 0x7fffffffULL) {
 			u64 count = (u64)cpu_khz * 1000;
 			do_div(count, 0x7fffffffUL);
@@ -685,8 +685,8 @@ static int setup_intel_arch_watchdog(voi
 	    (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 		goto fail;
 
-	perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
-	evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
+	perfctr_msr = MSR_ARCH_PERFMON_PERFCTR1;
+	evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL1;
 
 	if (!reserve_perfctr_nmi(perfctr_msr))
 		goto fail;
@@ -958,7 +958,7 @@ __kprobes int nmi_watchdog_tick(struct p
 	 			apic_write(APIC_LVTPC, APIC_DM_NMI);
 	 		}
 			else if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
-				 wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
+				 wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1) {
 				/* P6 based Pentium M need to re-unmask
 				 * the apic vector but it doesn't hurt
 				 * other P6 variant.
-- 
-Stephane
-
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