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Date: Mon, 19 Feb 2007 12:37:00 -0800 From: "Michael K. Edwards" <medwards.linux@...il.com> To: "Jose Goncalves" <jose.goncalves@...v.pt> Cc: "Frederik Deweerdt" <deweerdt@...e.fr>, akpm@...ux-foundation.org, linux-kernel@...r.kernel.org Subject: Re: Serial related oops What we've seen on our embedded ARM is that enabling an interrupt that is shared between multiple UARTs, at a stage when you have not set up all the data structures touched by the ISR and softirq, can have horrible consequences, including soft lockups and fandangos on core. You will be vulnerable to this unless you lock out the interrupt source (at the interrupt controller or, if you have to, globally) across the UART registration process in your platform's arch/mach-dependent core.c, in which case the TX irq test will of course fail. Roll-your-own SoC UARTs with bugs or "extended features" in IRQ enabling and delivery make things worse. I would love to see this disentangled in a maintainable way. It's such a nasty problem (especially given that bootloaders and early boot code frequently turn on one or more UARTs and leave them in an unknown state) that all we've been able to do so far is hack around it. I'll send an example patch when we've more or less isolated it, but it will be of limited use to you unless you have the exact set of UART warpage we do. Cheers, - Michael - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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