linux-kernel - Re: [PATCH] mm: PageLRU can be non-atomic bit operation

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Message-Id: <20070424112953.efa44e50.kamezawa.hiroyu@jp.fujitsu.com>
Date:	Tue, 24 Apr 2007 11:29:53 +0900
From:	KAMEZAWA Hiroyuki <kamezawa.hiroyu@...fujitsu.com>
To:	Hisashi Hifumi <hifumi.hisashi@....ntt.co.jp>
Cc:	hugh@...itas.com, akpm@...ux-foundation.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] mm: PageLRU can be non-atomic bit operation

On Tue, 24 Apr 2007 10:54:27 +0900
Hisashi Hifumi <hifumi.hisashi@....ntt.co.jp> wrote:
> In the case that changing the same bit concurrently, lock prefix or other
> spinlock is needed. But, I think that concurrent bit operation on different 
> bits
> is just like OR operation , so lock prefix is not needed.
> 
> AMD instruction manual says about bts that ,
> 
> "Copies a bit, specified by bit index in a register or 8-bit immediate 
> value (second operand), from a bit
> string (first operand), also called the bit base, to the carry flag (CF) of 
> the rFLAGS register, and then
> sets the bit in the bit string to 1."
> 
> BTS instruction is read-modify-write instruction on bit unit. So concurrent 
> bit operation on different
> bits may be possible.
> 
This is ia64's __set_bit() hehe..
==
static __inline__ void
__set_bit (int nr, volatile void *addr)
{
        *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
}
==

Bye.
-Kame

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