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Message-ID: <46338DBA.2050404@garzik.org>
Date: Sat, 28 Apr 2007 14:08:58 -0400
From: Jeff Garzik <jeff@...zik.org>
To: Andi Kleen <ak@...e.de>
CC: Simon Arlott <simon@...ott.org>,
Dave Jones <davej@...emonkey.org.uk>,
Alan Cox <alan@...rguk.ukuu.org.uk>,
linux-kernel@...r.kernel.org, patches@...-64.org
Subject: Re: [PATCH] [16/35] i386: Add an option for the VIA C7 which sets
appropriate L1 cache
Andi Kleen wrote:
> From: Simon Arlott <simon@...ott.org>
>
> The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has
> a cache line length of 64 according to
> http://www.digit-life.com/articles2/cpu/rmma-via-c7.html. This patch sets
> gcc to -march=686 and select s the correct cache shift.
>
> Signed-off-by: Simon Arlott <simon@...e.lp0.eu>
> Signed-off-by: Andi Kleen <ak@...e.de>
> Cc: Andi Kleen <ak@...e.de>
> Cc: Dave Jones <davej@...emonkey.org.uk>
> Cc: Alan Cox <alan@...rguk.ukuu.org.uk>
> Signed-off-by: Andrew Morton <akpm@...ux-foundation.org>
Has it been verified in the field that this CPU supports CMOV?
Jeff
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