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Date: Sat, 28 Apr 2007 14:28:55 -0400 From: Dave Jones <davej@...hat.com> To: Jeff Garzik <jeff@...zik.org> Cc: Andi Kleen <ak@...e.de>, Simon Arlott <simon@...ott.org>, Dave Jones <davej@...emonkey.org.uk>, Alan Cox <alan@...rguk.ukuu.org.uk>, linux-kernel@...r.kernel.org, patches@...-64.org Subject: Re: [PATCH] [16/35] i386: Add an option for the VIA C7 which sets appropriate L1 cache On Sat, Apr 28, 2007 at 02:08:58PM -0400, Jeff Garzik wrote: > Andi Kleen wrote: > > From: Simon Arlott <simon@...ott.org> > > > > The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has > > a cache line length of 64 according to > > http://www.digit-life.com/articles2/cpu/rmma-via-c7.html. This patch sets > > gcc to -march=686 and select s the correct cache shift. > > > > Signed-off-by: Simon Arlott <simon@...e.lp0.eu> > > Signed-off-by: Andi Kleen <ak@...e.de> > > Cc: Andi Kleen <ak@...e.de> > > Cc: Dave Jones <davej@...emonkey.org.uk> > > Cc: Alan Cox <alan@...rguk.ukuu.org.uk> > > Signed-off-by: Andrew Morton <akpm@...ux-foundation.org> > > Has it been verified in the field that this CPU supports CMOV? Yes. All their CPUs for some time now have done so. Dave -- http://www.codemonkey.org.uk - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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