linux-kernel - [PATCH] [19/26] i386: Enable bank 0 on non K7 Athlon

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Message-Id: <20070429234628.F1E2C151C5@wotan.suse.de>
Date:	Mon, 30 Apr 2007 01:46:28 +0200 (CEST)
From:	Andi Kleen <ak@...e.de>
To:	davej@...hat.com, patches@...-64.org, linux-kernel@...r.kernel.org
Subject: [PATCH] [19/26] i386: Enable bank 0 on non K7 Athlon


As a bug workaround bank 0 on K7s is normally disabled, but no need
to do that on other AMD CPUs.

Cc: davej@...hat.com

Signed-off-by: Andi Kleen <ak@...e.de>

---
 arch/i386/kernel/cpu/mcheck/k7.c |   10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

Index: linux/arch/i386/kernel/cpu/mcheck/k7.c
===================================================================
--- linux.orig/arch/i386/kernel/cpu/mcheck/k7.c
+++ linux/arch/i386/kernel/cpu/mcheck/k7.c
@@ -82,9 +82,13 @@ void amd_mcheck_init(struct cpuinfo_x86 
 	nr_mce_banks = l & 0xff;
 
 	/* Clear status for MC index 0 separately, we don't touch CTL,
-	 * as some Athlons cause spurious MCEs when its enabled. */
-	wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
-	for (i=1; i<nr_mce_banks; i++) {
+	 * as some K7 Athlons cause spurious MCEs when its enabled. */
+	if (boot_cpu_data.x86 == 6) {
+		wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
+		i = 1;
+	} else
+		i = 0;
+	for (; i<nr_mce_banks; i++) {
 		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 	}
-
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