linux-kernel - Re: PCIE

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Message-ID: <465A6742.4090903@zytor.com>
Date:	Sun, 27 May 2007 22:23:14 -0700
From:	"H. Peter Anvin" <hpa@...or.com>
To:	Grant Grundler <grundler@...isc-linux.org>
CC:	Roland Dreier <rdreier@...co.com>,
	David Miller <davem@...emloft.net>, abraham.manu@...il.com,
	greg@...ah.com, linux-pci@...ey.karlin.mff.cuni.cz,
	linux-kernel@...r.kernel.org
Subject: Re: PCIE

Grant Grundler wrote:
> On Sun, May 27, 2007 at 06:03:29PM -0700, Roland Dreier wrote:
> ...
>>  > I can imagine many systems where the cpu simply doesn't have enough
>>  > interrupt pins to uniquely identify every possible MSI interrupt
>>  > source.
>>
>> I have a hard time imagining a PCI host bus controller that converts
>> MSI interrupts back to wire interrupts that go to pins on the CPU.
>> For one thing it would be hard to maintain the guarantee that
>> MSI interrupts can't pass DMAs.
> 
> Whatever converts the MSI back to CPU IRQ pins would have to participate
> in the "cache coherency domain". This would avoid issues around DMA ordering.
> It _could_ be on the same silicon as the PCI Host bus controller as long
> as the above is true.
> 

Also, don't forget that a lot of platforms provide *no* hardware cache
coherency.

	-hpa
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