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Message-ID: <46656FD6.6030305@ru.mvista.com>
Date: Tue, 05 Jun 2007 18:14:46 +0400
From: Sergei Shtylyov <sshtylyov@...mvista.com>
To: Bartlomiej Zolnierkiewicz <bzolnier@...il.com>
Cc: Geller Sandor <wildy@...ra.hos.u-szeged.hu>,
Andrew Morton <akpm@...ux-foundation.org>,
linux-kernel@...r.kernel.org, linux-ide@...r.kernel.org
Subject: Re: HPT374 IDE problem with 2.6.21.* kernels
Hello, I wrote:
>> I felt inspired by this explanation (thanks!) and took a look at
>> hpt374-opensource-v2.10 vendor driver. Here is something interesting:
>> glbdata.c:
>> ...
>> #ifdef CLOCK_66MHZ
>> ULONG setting370_66[] = {
>> 0xd029d5e, 0xd029d26, 0xc829ca6, 0xc829c84, 0xc829c62,
>> 0x2c829d2c, 0x2c829c66, 0x2c829c62,
>> 0x1c829c62, 0x1c9a9c62, 0x1c929c62, 0x1c8e9c62, 0x1c8a9c62,
>> 0x1c8a9c62/*0x1cae9c62*/, 0x1c869c62, 0x1c869c62,
>> };
>> ...
>> hpt366.c:
>> ...
>> static u32 sixty_six_base_hpt37x[] = {
>> /* XFER_UDMA_6 */ 0x1c869c62,
>> /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
>> ...
>> So we are using Dual ATA Clock for UDMA5 whereas vendor driver doesn't
> This is so in all other HPT drivers (and HPT371N datasheet has the
> same figures -- this chip is the only one supporting UDMA6 and having
> the default DPLL clock > 50 MHz).
What I meant to say was the only one I have a datasheet for. :-)
MBR, Sergei
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