linux-kernel - Re: [PATCH] trim memory not covered by WB MTRRs

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Message-ID: <m1bqf3tu06.fsf@ebiederm.dsl.xmission.com>
Date:	Mon, 25 Jun 2007 18:54:49 -0600
From:	ebiederm@...ssion.com (Eric W. Biederman)
To:	Jesse Barnes <jesse.barnes@...el.com>
Cc:	Andi Kleen <andi@...stfloor.org>, linux-kernel@...r.kernel.org,
	akpm@...ux-foundation.org, Justin Piszcz <jpiszcz@...idpixels.com>,
	Yinghai Lu <yhlu.kernel@...il.com>
Subject: Re: [PATCH] trim memory not covered by WB MTRRs

Jesse Barnes <jesse.barnes@...el.com> writes:

> On Monday, June 25, 2007 4:34:33 Andi Kleen wrote:
>> > This patch fixes a bug in the last patch that caused the code to
>> > run on non-Intel machines (AMD machines apparently don't need it
>>
>> Actually the problem can happen on AMD too, but the symptoms can
>> be different and there can be more wrong than just the MTRRs.
>
> I should have been more specific in the changelog.  My understanding is 
> that AMD systems don't need it for memory above 4G, and since the code 
> doesn't handle holes (no test systems, nor any real reports that I've 
> seen), it's not that useful for finding problems below 4G.  We can 
> always change that later if needed though.

For the K7 and K8 cores AMD systems are exactly like Intel systems
with respect to MTRRs (although AMD systems also have additional registers)
For the K9 core (i.e. AMD socket F or the K8 with DDR2 support) there
is an additional mechanism that makes everything above 4G write-back
cacheable without using any MTRRs.

So only on the very latest AMD cpus would this code not be applicable.

Eric
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