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Message-ID: <Pine.LNX.4.64.0706271545490.3879@alien.or.mcafeemobile.com>
Date: Wed, 27 Jun 2007 16:30:15 -0700 (PDT)
From: Davide Libenzi <davidel@...ilserver.org>
To: Linus Torvalds <torvalds@...ux-foundation.org>
cc: Nick Piggin <nickpiggin@...oo.com.au>,
Eric Dumazet <dada1@...mosbay.com>,
Chuck Ebbert <cebbert@...hat.com>, Ingo Molnar <mingo@...e.hu>,
Jarek Poplawski <jarkao2@...pl>,
Miklos Szeredi <miklos@...redi.hu>, chris@...ee.ca,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
tglx@...utronix.de, Andrew Morton <akpm@...ux-foundation.org>
Subject: Re: [BUG] long freezes on thinkpad t60
On Wed, 27 Jun 2007, Linus Torvalds wrote:
> > IOW shouldn't an mfence always be there? Not only loads could leak up
> > into the wait phase, but stores too, if they have no dependency with the
> > "head" and "tail" loads.
>
> Stores never "leak up". They only ever leak down (ie past subsequent loads
> or stores), so you don't need to worry about them. That's actually already
> documented (although not in those terms), and if it wasn't true, then we
> couldn't do the spin unlock with just a regular store anyway.
Yes, Intel has never done that. They'll probably never do it since it'll
break a lot of system software (unless they use a new mode-bit that
allows system software to enable lose-ordering). Although I clearly
remember to have read in one of their P4 optimization manuals to not
assume this in the future.
- Davide
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