linux-kernel - Re: New format Intel microcode...

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Date:	Thu, 28 Jun 2007 07:12:55 -0700
From:	Arjan van de Ven <arjan@...ux.intel.com>
To:	Bill Davidsen <davidsen@....com>
Cc:	Andi Kleen <andi@...stfloor.org>,
	Daniel J Blueman <daniel.blueman@...il.com>,
	Shaohua Li <shaohua.li@...el.com>, jamagallon@....com,
	tigran@...azian.fsnet.co.uk,
	Linux Kernel <linux-kernel@...r.kernel.org>
Subject: Re: New format Intel microcode...

(while I work for Intel this is not an official Intel statement, but
there is so much FUD going around now that I feel I need to at least
point out a few things others "forget")
> > 
> Slashdot carried an article this morning saying that an error in Intel 
> microcode was being fixed.

don't just always believe everything you read on slashdot please

>  However, it listed only Windows related sites 
> for the "fix" download. Is this the same TLB issue? And are these really 
> fixes for Windows to flush the TLB properly the way Linux does?

First of all, Linux has microcode updates as well. Some of the more
hypish news-bulletins just conveniently "forgot" about this. Basically
all distributions ship them, so users who use the distro update tools
get these automatically. And the update mentioned has been shipping for
a while (in version 1.17).

Second, Intel really recommends always running the latest microcode.
(which is easy on Linux at least, and on Windows you can now see how
they do it). While reading the errata list may sound really scary, most
of the issues found and fixed are "lab finds" and are things operating
systems don't do. Some are more visible though; and since it's easy to
get the latest microcode (yum upgrade / apt-get upgrade / etc) you
probably are already running a recent one.

As for the TLB behavior; the Linux kernel is behaving correctly for
quite a while now as far as I know.. I wouldn't worry about it too much.
SMP tlb shootdown always has been tricky in the light of multiple cpus
having tlbs "hot" and active while tearing down mappings. 
(just think about it: cpu0 is accessing the memory while cpu1 is
removing it; until you flush the tlb on cpu0 it won't see the new
pagetable state since the tlb is a cache...)

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