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Message-ID: <5FD5754DDBA0B1499B5A0B4BB5419485015CC88A@fmsmsx411.amr.corp.intel.com>
Date:	Fri, 6 Jul 2007 10:50:30 -0700
From:	"Li, Tong N" <tong.n.li@...el.com>
To:	"Andi Kleen" <andi@...stfloor.org>,
	"Andrew Morton" <akpm@...ux-foundation.org>
Cc:	"Mathieu Desnoyers" <mathieu.desnoyers@...ymtl.ca>,
	"Alexey Dobriyan" <adobriyan@...il.com>,
	<linux-kernel@...r.kernel.org>
Subject: RE: [patch 10/10] Scheduler profiling - Use immediate values

> Also cache misses in this situation tend to be much more than 48
cycles
> (even an K8 with integrated memory controller with fastest DIMMs is
> slower than that)  Mathieu probably measured an L2 miss, not a load
from
> RAM.
> Load from RAM can be hundreds of ns in the worst case.
> 

The 48 cycles sounds to me like a memory load in an unloaded system, but
it is quite low. I wonder how it was measured...

  tong
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