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Message-Id: <20070706092022.b9b5fbcc.kamezawa.hiroyu@jp.fujitsu.com>
Date:	Fri, 6 Jul 2007 09:20:22 +0900
From:	KAMEZAWA Hiroyuki <kamezawa.hiroyu@...fujitsu.com>
To:	KAMEZAWA Hiroyuki <kamezawa.hiroyu@...fujitsu.com>
Cc:	Mike Stroyan <mike@...oyan.net>, linux-ia64@...r.kernel.org,
	linux-kernel@...r.kernel.org, tony.luck@...el.com,
	linux-mm@...ck.org, clameter@....com, y-goto@...fujitsu.com,
	dmosberger@...il.com, hugh@...itas.com, nickpiggin@...oo.com.au
Subject: Re: [BUGFIX][PATCH] DO flush icache before set_pte() on ia64.

On Fri, 6 Jul 2007 07:18:53 +0900
KAMEZAWA Hiroyuki <kamezawa.hiroyu@...fujitsu.com> wrote:

> On Thu, 5 Jul 2007 12:13:09 -0600
> Mike Stroyan <mike@...oyan.net> wrote:
> >   The L3 cache is involved in the HP-UX defect description because the
> > earlier HP-UX patch PHKL_33781 added flushing of the instruction cache
> > when an executable mapping was removed.  Linux never added that
> > unsuccessfull attempt at montecito cache coherency.  In the current
> > linux situation it can execute old cache lines straight from L2 icache.
> > 
> Hmm... I couldn't understand "why icache includes old lines in a new page."
> This happens at
>  - a file is newly loaded into page-cache.
>  - only on NFS.
>  - happens very *often* if the program is unlucky.
> 
> So I wrote my understainding as I think.
> 
I'll remove reference to HP-UX in the next post. And rewrite all description.

> > 
> >   The only defect that I see in the current implementation of
> > lazy_mmu_prot_update() is that it is called too late in some
> > functions that are already calling it.  Are your large changes
> > attempting to correct other defects?  Or are you simplifying
> > away potentially valuable code because you don't understand it?
> > 
> I know your *simple* patch in April wasn't included. So I wrote this.
> In April thread, commenter's advices was "implement flush_icache_page()" I think.  
> If you have a better patch, please post.
> 
I'll check callers of lazy_mmu_prot_update() again and remove uncecessary calls.
But, basically, i-cache flush will be necessary when VM_EXEC is on. PG_arch_1 will
help us for optimization.

-Kame




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